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Searched +full:da830 +full:- +full:cfgchip (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dda8xx-cfgchip.txt1 Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
3 TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
7 All of the clock nodes described below must be child nodes of a CFGCHIP node
8 (compatible = "ti,da830-cfgchip").
11 --------------
13 - compatible: shall be "ti,da830-usb-phy-clocks".
14 - #clock-cells: from common clock binding; shall be set to 1.
15 - clocks: phandles to the parent clocks corresponding to clock-names
16 - clock-names: shall be "fck", "usb_refclkin", "auxclk"
22 ------------------------------
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/linux/drivers/clk/davinci/
H A Dda8xx-cfgchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
8 #include <linux/clk-provider.h>
12 #include <linux/mfd/da8xx-cfgchip.h>
15 #include <linux/platform_data/clk-da8xx-cfgchip.h>
21 /* --- Gate clocks --- */
27 u32 cfgchip; member
46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); in da8xx_cfgchip_gate_clk_enable()
53 regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); in da8xx_cfgchip_gate_clk_disable()
61 regmap_read(clk->regmap, clk->reg, &val); in da8xx_cfgchip_gate_clk_is_enabled()
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H A Dpll-da850.c1 // SPDX-License-Identifier: GPL-2.0
3 * PLL clock descriptions for TI DA850/OMAP-L138/AM18XX
9 #include <linux/clk-provider.h>
16 #include <linux/mfd/da8xx-cfgchip.h>
31 .unlock_reg = CFGCHIP(0),
89 int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in da850_pll0_init() argument
93 davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); in da850_pll0_init()
96 clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0"); in da850_pll0_init()
99 clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0"); in da850_pll0_init()
100 clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1"); in da850_pll0_init()
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H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
78 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
85 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
89 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
95 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
120 mult = readl(pll->base + PLLM) & pll->pllm_mask; in davinci_pll_recalc_rate()
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/linux/Documentation/devicetree/bindings/phy/
H A Dti,da830-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,da830-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DA8xx/OMAP-L1xx/AM18xx USB PHY
10 - David Lechner <david@lechnology.com>
16 It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
22 - const: ti,da830-usb-phy
24 '#phy-cells':
33 clock-names:
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/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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