Lines Matching +full:da830 +full:- +full:cfgchip

1 // SPDX-License-Identifier: GPL-2.0
3 * PLL clock descriptions for TI DA850/OMAP-L138/AM18XX
9 #include <linux/clk-provider.h>
16 #include <linux/mfd/da8xx-cfgchip.h>
31 .unlock_reg = CFGCHIP(0),
89 int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in da850_pll0_init() argument
93 davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); in da850_pll0_init()
96 clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0"); in da850_pll0_init()
99 clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0"); in da850_pll0_init()
100 clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1"); in da850_pll0_init()
101 clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc"); in da850_pll0_init()
104 clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc"); in da850_pll0_init()
107 clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc0"); in da850_pll0_init()
108 clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc1"); in da850_pll0_init()
113 clk_register_clkdev(clk, "pll0_sysclk6", "da850-psc0"); in da850_pll0_init()
124 clk_register_clkdev(clk, NULL, "davinci-wdt"); in da850_pll0_init()
145 struct regmap *cfgchip; in of_da850_pll0_init() local
153 cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); in of_da850_pll0_init()
157 da850_pll0_sysclk_info, 7, base, cfgchip); in of_da850_pll0_init()
162 .unlock_reg = CFGCHIP(3),
198 int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in da850_pll1_init() argument
202 davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip); in da850_pll1_init()
207 clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc"); in da850_pll1_init()
223 int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in of_da850_pll1_init() argument
225 return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info, in of_da850_pll1_init()
227 da850_pll1_sysclk_info, 3, base, cfgchip); in of_da850_pll1_init()