1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27properties: 28 riscv,isa: 29 description: 30 Identifies the specific RISC-V instruction set architecture 31 supported by the hart. These are documented in the RISC-V 32 User-Level ISA document, available from 33 https://riscv.org/specifications/ 34 35 Due to revisions of the ISA specification, some deviations 36 have arisen over time. 37 Notably, riscv,isa was defined prior to the creation of the 38 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 39 implies "zicntr_zicsr_zifencei_zihpm". 40 41 While the isa strings in ISA specification are case 42 insensitive, letters in the riscv,isa string must be all 43 lowercase. 44 $ref: /schemas/types.yaml#/definitions/string 45 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 46 deprecated: true 47 48 riscv,isa-base: 49 description: 50 The base ISA implemented by this hart, as described by the 20191213 51 version of the unprivileged ISA specification. 52 enum: 53 - rv32i 54 - rv64i 55 56 riscv,isa-extensions: 57 $ref: /schemas/types.yaml#/definitions/string-array 58 minItems: 1 59 description: Extensions supported by the hart. 60 items: 61 anyOf: 62 # single letter extensions, in canonical order 63 - const: i 64 description: | 65 The base integer instruction set, as ratified in the 20191213 66 version of the unprivileged ISA specification. 67 68 This does not include Chapter 10, "Counters", which was moved into 69 the Zicntr and Zihpm extensions after the ratification of the 70 20191213 version of the unprivileged specification. 71 72 - const: m 73 description: 74 The standard M extension for integer multiplication and division, as 75 ratified in the 20191213 version of the unprivileged ISA 76 specification. 77 78 - const: a 79 description: 80 The standard A extension for atomic instructions, as ratified in the 81 20191213 version of the unprivileged ISA specification. 82 83 - const: f 84 description: 85 The standard F extension for single-precision floating point, as 86 ratified in the 20191213 version of the unprivileged ISA 87 specification. 88 89 - const: d 90 description: 91 The standard D extension for double-precision floating-point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: q 96 description: 97 The standard Q extension for quad-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: c 102 description: 103 The standard C extension for compressed instructions, as ratified in 104 the 20191213 version of the unprivileged ISA specification. 105 106 - const: b 107 description: 108 The standard B extension for bit manipulation instructions, as 109 ratified in the 20240411 version of the unprivileged ISA 110 specification. The B standard extension comprises instructions 111 provided by the Zba, Zbb, and Zbs extensions. 112 113 - const: v 114 description: 115 The standard V extension for vector operations, as ratified 116 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 117 encoding") of the riscv-v-spec. 118 119 - const: h 120 description: 121 The standard H extension for hypervisors as ratified in the RISC-V 122 Instruction Set Manual, Volume II Privileged Architecture, 123 Document Version 20211203. 124 125 # multi-letter extensions, sorted alphanumerically 126 - const: sha 127 description: | 128 The standard Sha extension for augmented hypervisor extension as 129 ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 130 ("rva23/rvb23 ratified"). 131 132 Sha captures the full set of features that are mandated to be 133 supported along with the H extension. Sha comprises the following 134 extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, 135 Shvstvecd, and Ssstateen. 136 137 - const: shcounterenw 138 description: | 139 The standard Shcounterenw extension for support writable enables 140 in hcounteren for any supported counter, as ratified in RISC-V 141 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 142 ratified state.") 143 144 - const: shgatpa 145 description: | 146 The standard Shgatpa extension indicates that for each supported 147 virtual memory scheme SvNN supported in satp, the corresponding 148 hgatp SvNNx4 mode must be supported. The hgatp mode Bare must 149 also be supported. It is ratified in RISC-V Profiles Version 1.0, 150 with commit b1d806605f87 ("Updated to ratified state.") 151 152 - const: shtvala 153 description: | 154 The standard Shtvala extension for htval be written with the 155 faulting guest physical address in all circumstances permitted by 156 the ISA. It is ratified in RISC-V Profiles Version 1.0, with 157 commit b1d806605f87 ("Updated to ratified state.") 158 159 - const: shvsatpa 160 description: | 161 The standard Shvsatpa extension for vsatp supporting all translation 162 modes supported in satp, as ratified in RISC-V Profiles Version 1.0, 163 with commit b1d806605f87 ("Updated to ratified state.") 164 165 - const: shvstvala 166 description: | 167 The standard Shvstvala extension for vstval provides all needed 168 values as ratified in RISC-V Profiles Version 1.0, with commit 169 b1d806605f87 ("Updated to ratified state.") 170 171 - const: shvstvecd 172 description: | 173 The standard Shvstvecd extension for vstvec supporting Direct mode, 174 as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 175 ("Updated to ratified state.") 176 177 - const: smaia 178 description: | 179 The standard Smaia supervisor-level extension for the advanced 180 interrupt architecture for machine-mode-visible csr and behavioural 181 changes to interrupts as frozen at commit ccbddab ("Merge pull 182 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 183 184 - const: smcdeleg 185 description: | 186 The standard Smcdeleg machine-level extension for the machine mode 187 to delegate the hpmcounters to supervisor mode so that they are 188 directly accessible in the supervisor mode as ratified in the 189 20240213 version of the privileged ISA specification. 190 191 - const: smcntrpmf 192 description: | 193 The standard Smcntrpmf machine-level extension for the machine mode 194 to enable privilege mode filtering for cycle and instret counters as 195 ratified in the 20240326 version of the privileged ISA specification. 196 197 - const: smcsrind 198 description: | 199 The standard Smcsrind machine-level extension extends the 200 indirect CSR access mechanism defined by the Smaia extension. This 201 extension allows other ISA extensions to use indirect CSR access 202 mechanism in M-mode as ratified in the 20240326 version of the 203 privileged ISA specification. 204 205 - const: smmpm 206 description: | 207 The standard Smmpm extension for M-mode pointer masking as 208 ratified at commit d70011dde6c2 ("Update to ratified state") 209 of riscv-j-extension. 210 211 - const: smnpm 212 description: | 213 The standard Smnpm extension for next-mode pointer masking as 214 ratified at commit d70011dde6c2 ("Update to ratified state") 215 of riscv-j-extension. 216 217 - const: smstateen 218 description: | 219 The standard Smstateen extension for controlling access to CSRs 220 added by other RISC-V extensions in H/S/VS/U/VU modes and as 221 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 222 223 - const: ssaia 224 description: | 225 The standard Ssaia supervisor-level extension for the advanced 226 interrupt architecture for supervisor-mode-visible csr and 227 behavioural changes to interrupts as frozen at commit ccbddab 228 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 229 230 - const: ssccfg 231 description: | 232 The standard Ssccfg supervisor-level extension for configuring 233 the delegated hpmcounters to be accessible directly in supervisor 234 mode as ratified in the 20240213 version of the privileged ISA 235 specification. This extension depends on Sscsrind, Smcdeleg, Zihpm, 236 Zicntr extensions. 237 238 - const: ssccptr 239 description: | 240 The standard Ssccptr extension for main memory (cacheability and 241 coherence) hardware page-table reads, as ratified in RISC-V 242 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 243 ratified state.") 244 245 - const: sscofpmf 246 description: | 247 The standard Sscofpmf supervisor-level extension for count overflow 248 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 249 to manually trigger workflow. (#2)") of riscv-count-overflow. 250 251 - const: sscounterenw 252 description: | 253 The standard Sscounterenw extension for support writable enables 254 in scounteren for any supported counter, as ratified in RISC-V 255 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 256 ratified state.") 257 258 - const: sscsrind 259 description: | 260 The standard Sscsrind supervisor-level extension extends the 261 indirect CSR access mechanism defined by the Ssaia extension. This 262 extension allows other ISA extensions to use indirect CSR access 263 mechanism in S-mode as ratified in the 20240326 version of the 264 privileged ISA specification. 265 266 - const: ssnpm 267 description: | 268 The standard Ssnpm extension for next-mode pointer masking as 269 ratified at commit d70011dde6c2 ("Update to ratified state") 270 of riscv-j-extension. 271 272 - const: ssqosid 273 description: | 274 The standard Ssqosid extension for Quality of Service ID is 275 ratified as v1.0 in commit d9c616497fde ("Merge pull 276 request #7 from ved-rivos/Ratified") of riscv-ssqosid. 277 278 - const: ssstateen 279 description: | 280 The standard Ssstateen extension for supervisor-mode view of the 281 state-enable extension, as ratified in RISC-V Profiles Version 1.0, 282 with commit b1d806605f87 ("Updated to ratified state.") 283 284 - const: sstc 285 description: | 286 The standard Sstc supervisor-level extension for time compare as 287 ratified at commit 3f9ed34 ("Add ability to manually trigger 288 workflow. (#2)") of riscv-time-compare. 289 290 - const: sstvala 291 description: | 292 The standard Sstvala extension for stval provides all needed values 293 as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 294 ("Updated to ratified state.") 295 296 - const: sstvecd 297 description: | 298 The standard Sstvecd extension for stvec supports Direct mode as 299 ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 300 ("Updated to ratified state.") 301 302 - const: ssu64xl 303 description: | 304 The standard Ssu64xl extension for UXLEN=64 must be supported, as 305 ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 306 ("Updated to ratified state.") 307 308 - const: supm 309 description: | 310 The standard Supm extension for pointer masking support in user 311 mode (U-mode) as ratified at commit d70011dde6c2 ("Update to 312 ratified state") of riscv-j-extension. 313 314 Supm represents a combination of underlying hardware capability 315 (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode 316 software configuration that enables pointer masking for U-mode. 317 318 DO NOT include this property in device trees targeting privileged 319 system software (S-mode or M-mode). 320 321 This property is only appropriate in device trees provided to 322 U-mode software where the next-higher-privilege-mode supports 323 Smnpm or Ssnpm and enables it for U-mode. 324 325 - const: svade 326 description: | 327 The standard Svade supervisor-level extension for SW-managed PTE A/D 328 bit updates as ratified in the 20240213 version of the privileged 329 ISA specification. 330 331 Both Svade and Svadu extensions control the hardware behavior when 332 the PTE A/D bits need to be set. The default behavior for the four 333 possible combinations of these extensions in the device tree are: 334 1) Neither Svade nor Svadu present in DT => It is technically 335 unknown whether the platform uses Svade or Svadu. Supervisor 336 software should be prepared to handle either hardware updating 337 of the PTE A/D bits or page faults when they need updated. 338 2) Only Svade present in DT => Supervisor must assume Svade to be 339 always enabled. 340 3) Only Svadu present in DT => Supervisor must assume Svadu to be 341 always enabled. 342 4) Both Svade and Svadu present in DT => Supervisor must assume 343 Svadu turned-off at boot time. To use Svadu, supervisor must 344 explicitly enable it using the SBI FWFT extension. 345 346 - const: svadu 347 description: | 348 The standard Svadu supervisor-level extension for hardware updating 349 of PTE A/D bits as ratified in the 20240528 version of the 350 privileged ISA specification. Please refer to Svade dt-binding 351 description for more details. 352 353 - const: svinval 354 description: 355 The standard Svinval supervisor-level extension for fine-grained 356 address-translation cache invalidation as ratified in the RISC-V 357 Instruction Set Manual, Volume II Privileged Architecture, 358 Document Version 20211203. 359 360 - const: svnapot 361 description: 362 The standard Svnapot supervisor-level extensions for napot 363 translation contiguity as ratified in the RISC-V Instruction Set 364 Manual, Volume II Privileged Architecture, Document Version 365 20211203. 366 367 - const: svpbmt 368 description: 369 The standard Svpbmt supervisor-level extensions for page-based 370 memory types as ratified in the RISC-V Instruction Set Manual, 371 Volume II Privileged Architecture, Document Version 20211203. 372 373 - const: svrsw60t59b 374 description: 375 The Svrsw60t59b extension for providing two more bits[60:59] to 376 PTE/PMD entry as ratified at commit 28bde925e7a7 ("PTE Reserved 377 for SW bits 60:59") of riscv-non-isa/riscv-iommu. 378 379 - const: svvptc 380 description: 381 The standard Svvptc supervisor-level extension for 382 address-translation cache behaviour with respect to invalid entries 383 as ratified at commit 4a69197e5617 ("Update to ratified state") of 384 riscv-svvptc. 385 386 - const: za64rs 387 description: 388 The standard Za64rs extension for reservation set size of at most 389 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit 390 b1d806605f87 ("Updated to ratified state.") 391 392 - const: zaamo 393 description: | 394 The standard Zaamo extension for atomic memory operations as 395 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 396 (#1304)") of the unprivileged ISA specification. 397 398 - const: zabha 399 description: | 400 The Zabha extension for Byte and Halfword Atomic Memory Operations 401 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 402 riscv-zabha. 403 404 - const: zacas 405 description: | 406 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 407 is supported as ratified at commit 5059e0ca641c ("update to 408 ratified") of the riscv-zacas. 409 410 - const: zalasr 411 description: | 412 The standard Zalasr extension for load-acquire/store-release as frozen 413 at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. 414 415 - const: zalrsc 416 description: | 417 The standard Zalrsc extension for load-reserved/store-conditional as 418 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 419 (#1304)") of the unprivileged ISA specification. 420 421 - const: zawrs 422 description: | 423 The Zawrs extension for entering a low-power state or for trapping 424 to a hypervisor while waiting on a store to a memory location, as 425 ratified in commit 98918c844281 ("Merge pull request #1217 from 426 riscv/zawrs") of riscv-isa-manual. 427 428 - const: zba 429 description: | 430 The standard Zba bit-manipulation extension for address generation 431 acceleration instructions as ratified at commit 6d33919 ("Merge pull 432 request #158 from hirooih/clmul-fix-loop-end-condition") of 433 riscv-bitmanip. 434 435 - const: zbb 436 description: | 437 The standard Zbb bit-manipulation extension for basic bit-manipulation 438 as ratified at commit 6d33919 ("Merge pull request #158 from 439 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 440 441 - const: zbc 442 description: | 443 The standard Zbc bit-manipulation extension for carry-less 444 multiplication as ratified at commit 6d33919 ("Merge pull request 445 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 446 447 - const: zbkb 448 description: 449 The standard Zbkb bitmanip instructions for cryptography as ratified 450 in version 1.0 of RISC-V Cryptography Extensions Volume I 451 specification. 452 453 - const: zbkc 454 description: 455 The standard Zbkc carry-less multiply instructions as ratified 456 in version 1.0 of RISC-V Cryptography Extensions Volume I 457 specification. 458 459 - const: zbkx 460 description: 461 The standard Zbkx crossbar permutation instructions as ratified 462 in version 1.0 of RISC-V Cryptography Extensions Volume I 463 specification. 464 465 - const: zbs 466 description: | 467 The standard Zbs bit-manipulation extension for single-bit 468 instructions as ratified at commit 6d33919 ("Merge pull request #158 469 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 470 471 - const: zca 472 description: | 473 The Zca extension part of Zc* standard extensions for code size 474 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 475 RV64 as it contains no instructions") of riscv-code-size-reduction, 476 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 477 of zc.adoc to src tree."). 478 479 - const: zcb 480 description: | 481 The Zcb extension part of Zc* standard extensions for code size 482 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 483 RV64 as it contains no instructions") of riscv-code-size-reduction, 484 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 485 of zc.adoc to src tree."). 486 487 - const: zcd 488 description: | 489 The Zcd extension part of Zc* standard extensions for code size 490 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 491 RV64 as it contains no instructions") of riscv-code-size-reduction, 492 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 493 of zc.adoc to src tree."). 494 495 - const: zcf 496 description: | 497 The Zcf extension part of Zc* standard extensions for code size 498 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 499 RV64 as it contains no instructions") of riscv-code-size-reduction, 500 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 501 of zc.adoc to src tree."). 502 503 - const: zclsd 504 description: 505 The Zclsd extension implements the compressed (16-bit) version of the 506 Load/Store Pair for RV32. As with Zilsd, this extension was ratified 507 in commit f88abf1 ("Integrating load/store pair for RV32 with the 508 main manual") of riscv-isa-manual. 509 510 - const: zcmop 511 description: 512 The standard Zcmop extension version 1.0, as ratified in commit 513 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 514 515 - const: zfa 516 description: 517 The standard Zfa extension for additional floating point 518 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 519 riscv-isa-manual. 520 521 - const: zfbfmin 522 description: 523 The standard Zfbfmin extension which provides minimal support for 524 16-bit half-precision brain floating-point instructions, as ratified 525 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 526 527 - const: zfh 528 description: 529 The standard Zfh extension for 16-bit half-precision binary 530 floating-point instructions, as ratified in commit 64074bc ("Update 531 version numbers for Zfh/Zfinx") of riscv-isa-manual. 532 533 - const: zfhmin 534 description: 535 The standard Zfhmin extension which provides minimal support for 536 16-bit half-precision binary floating-point instructions, as ratified 537 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 538 riscv-isa-manual. 539 540 - const: zicbom 541 description: 542 The standard Zicbom extension for base cache management operations as 543 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 544 545 - const: zicbop 546 description: 547 The standard Zicbop extension for cache-block prefetch instructions 548 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 549 riscv-CMOs. 550 551 - const: zicboz 552 description: 553 The standard Zicboz extension for cache-block zeroing as ratified 554 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 555 556 - const: ziccamoa 557 description: 558 The standard Ziccamoa extension for main memory (cacheability and 559 coherence) must support all atomics in A, as ratified in RISC-V 560 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 561 ratified state.") 562 563 - const: ziccif 564 description: 565 The standard Ziccif extension for main memory (cacheability and 566 coherence) instruction fetch atomicity, as ratified in RISC-V 567 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 568 ratified state.") 569 570 - const: zicclsm 571 description: 572 The standard Zicclsm extension for main memory (cacheability and 573 coherence) must support misaligned loads and stores, as ratified 574 in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated 575 to ratified state.") 576 577 - const: ziccrse 578 description: 579 The standard Ziccrse extension which provides forward progress 580 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 581 ("Updated to ratified state.") of the riscv profiles specification. 582 583 - const: zicfilp 584 description: | 585 The standard Zicfilp extension for enforcing forward edge 586 control-flow integrity as ratified in commit 3f8e450 ("merge 587 pull request #227 from ved-rivos/0709") of riscv-cfi 588 github repo. 589 590 - const: zicfiss 591 description: | 592 The standard Zicfiss extension for enforcing backward edge 593 control-flow integrity as ratified in commit 3f8e450 ("merge 594 pull request #227 from ved-rivos/0709") of riscv-cfi 595 github repo. 596 597 - const: zicntr 598 description: 599 The standard Zicntr extension for base counters and timers, as 600 ratified in the 20191213 version of the unprivileged ISA 601 specification. 602 603 - const: zicond 604 description: 605 The standard Zicond extension for conditional arithmetic and 606 conditional-select/move operations as ratified in commit 95cf1f9 607 ("Add changes requested by Ved during signoff") of riscv-zicond. 608 609 - const: zicsr 610 description: | 611 The standard Zicsr extension for control and status register 612 instructions, as ratified in the 20191213 version of the 613 unprivileged ISA specification. 614 615 This does not include Chapter 10, "Counters", which documents 616 special case read-only CSRs, that were moved into the Zicntr and 617 Zihpm extensions after the ratification of the 20191213 version of 618 the unprivileged specification. 619 620 - const: zifencei 621 description: 622 The standard Zifencei extension for instruction-fetch fence, as 623 ratified in the 20191213 version of the unprivileged ISA 624 specification. 625 626 - const: zihintntl 627 description: 628 The standard Zihintntl extension for non-temporal locality hints, as 629 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 630 riscv-isa-manual. 631 632 - const: zihintpause 633 description: 634 The standard Zihintpause extension for pause hints, as ratified in 635 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 636 637 - const: zihpm 638 description: 639 The standard Zihpm extension for hardware performance counters, as 640 ratified in the 20191213 version of the unprivileged ISA 641 specification. 642 643 - const: zilsd 644 description: 645 The standard Zilsd extension which provides support for aligned 646 register-pair load and store operations in 32-bit instruction 647 encodings, as ratified in commit f88abf1 ("Integrating 648 load/store pair for RV32 with the main manual") of riscv-isa-manual. 649 650 - const: zimop 651 description: 652 The standard Zimop extension version 1.0, as ratified in commit 653 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 654 655 - const: zk 656 description: 657 The standard Zk Standard Scalar cryptography extension as ratified 658 in version 1.0 of RISC-V Cryptography Extensions Volume I 659 specification. 660 661 - const: zkn 662 description: 663 The standard Zkn NIST algorithm suite extensions as ratified in 664 version 1.0 of RISC-V Cryptography Extensions Volume I 665 specification. 666 667 - const: zknd 668 description: | 669 The standard Zknd for NIST suite: AES decryption instructions as 670 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 671 specification. 672 673 - const: zkne 674 description: | 675 The standard Zkne for NIST suite: AES encryption instructions as 676 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 677 specification. 678 679 - const: zknh 680 description: | 681 The standard Zknh for NIST suite: hash function instructions as 682 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 683 specification. 684 685 - const: zkr 686 description: 687 The standard Zkr entropy source extension as ratified in version 688 1.0 of RISC-V Cryptography Extensions Volume I specification. 689 This string being present means that the CSR associated to this 690 extension is accessible at the privilege level to which that 691 device-tree has been provided. 692 693 - const: zks 694 description: 695 The standard Zks ShangMi algorithm suite extensions as ratified in 696 version 1.0 of RISC-V Cryptography Extensions Volume I 697 specification. 698 699 - const: zksed 700 description: | 701 The standard Zksed for ShangMi suite: SM4 block cipher instructions 702 as ratified in version 1.0 of RISC-V Cryptography Extensions 703 Volume I specification. 704 705 - const: zksh 706 description: | 707 The standard Zksh for ShangMi suite: SM3 hash function instructions 708 as ratified in version 1.0 of RISC-V Cryptography Extensions 709 Volume I specification. 710 711 - const: zkt 712 description: 713 The standard Zkt for data independent execution latency as ratified 714 in version 1.0 of RISC-V Cryptography Extensions Volume I 715 specification. 716 717 - const: ztso 718 description: 719 The standard Ztso extension for total store ordering, as ratified 720 in commit 2e5236 ("Ztso is now ratified.") of the 721 riscv-isa-manual. 722 723 - const: zvbb 724 description: 725 The standard Zvbb extension for vectored basic bit-manipulation 726 instructions, as ratified in commit 56ed795 ("Update 727 riscv-crypto-spec-vector.adoc") of riscv-crypto. 728 729 - const: zvbc 730 description: 731 The standard Zvbc extension for vectored carryless multiplication 732 instructions, as ratified in commit 56ed795 ("Update 733 riscv-crypto-spec-vector.adoc") of riscv-crypto. 734 735 - const: zve32f 736 description: 737 The standard Zve32f extension for embedded processors, as ratified 738 in commit 6f702a2 ("Vector extensions are now ratified") of 739 riscv-v-spec. 740 741 - const: zve32x 742 description: 743 The standard Zve32x extension for embedded processors, as ratified 744 in commit 6f702a2 ("Vector extensions are now ratified") of 745 riscv-v-spec. 746 747 - const: zve64d 748 description: 749 The standard Zve64d extension for embedded processors, as ratified 750 in commit 6f702a2 ("Vector extensions are now ratified") of 751 riscv-v-spec. 752 753 - const: zve64f 754 description: 755 The standard Zve64f extension for embedded processors, as ratified 756 in commit 6f702a2 ("Vector extensions are now ratified") of 757 riscv-v-spec. 758 759 - const: zve64x 760 description: 761 The standard Zve64x extension for embedded processors, as ratified 762 in commit 6f702a2 ("Vector extensions are now ratified") of 763 riscv-v-spec. 764 765 - const: zvfbfmin 766 description: 767 The standard Zvfbfmin extension for minimal support for vectored 768 16-bit half-precision brain floating-point instructions, as ratified 769 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 770 771 - const: zvfbfwma 772 description: 773 The standard Zvfbfwma extension for vectored half-precision brain 774 floating-point widening multiply-accumulate instructions, as ratified 775 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 776 777 - const: zvfh 778 description: 779 The standard Zvfh extension for vectored half-precision 780 floating-point instructions, as ratified in commit e2ccd05 781 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 782 783 - const: zvfhmin 784 description: 785 The standard Zvfhmin extension for vectored minimal half-precision 786 floating-point instructions, as ratified in commit e2ccd05 787 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 788 789 - const: zvkb 790 description: 791 The standard Zvkb extension for vector cryptography bit-manipulation 792 instructions, as ratified in commit 56ed795 ("Update 793 riscv-crypto-spec-vector.adoc") of riscv-crypto. 794 795 - const: zvkg 796 description: 797 The standard Zvkg extension for vector GCM/GMAC instructions, as 798 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 799 of riscv-crypto. 800 801 - const: zvkn 802 description: 803 The standard Zvkn extension for NIST algorithm suite instructions, as 804 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 805 of riscv-crypto. 806 807 - const: zvknc 808 description: 809 The standard Zvknc extension for NIST algorithm suite with carryless 810 multiply instructions, as ratified in commit 56ed795 ("Update 811 riscv-crypto-spec-vector.adoc") of riscv-crypto. 812 813 - const: zvkned 814 description: 815 The standard Zvkned extension for Vector AES block cipher 816 instructions, as ratified in commit 56ed795 ("Update 817 riscv-crypto-spec-vector.adoc") of riscv-crypto. 818 819 - const: zvkng 820 description: 821 The standard Zvkng extension for NIST algorithm suite with GCM 822 instructions, as ratified in commit 56ed795 ("Update 823 riscv-crypto-spec-vector.adoc") of riscv-crypto. 824 825 - const: zvknha 826 description: | 827 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 828 hash (SHA-256 only) instructions, as ratified in commit 829 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 830 831 - const: zvknhb 832 description: | 833 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 834 hash (SHA-256 and SHA-512) instructions, as ratified in commit 835 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 836 837 - const: zvks 838 description: 839 The standard Zvks extension for ShangMi algorithm suite 840 instructions, as ratified in commit 56ed795 ("Update 841 riscv-crypto-spec-vector.adoc") of riscv-crypto. 842 843 - const: zvksc 844 description: 845 The standard Zvksc extension for ShangMi algorithm suite with 846 carryless multiplication instructions, as ratified in commit 56ed795 847 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 848 849 - const: zvksed 850 description: | 851 The standard Zvksed extension for ShangMi suite: SM4 block cipher 852 instructions, as ratified in commit 56ed795 ("Update 853 riscv-crypto-spec-vector.adoc") of riscv-crypto. 854 855 - const: zvksg 856 description: 857 The standard Zvksg extension for ShangMi algorithm suite with GCM 858 instructions, as ratified in commit 56ed795 ("Update 859 riscv-crypto-spec-vector.adoc") of riscv-crypto. 860 861 - const: zvksh 862 description: | 863 The standard Zvksh extension for ShangMi suite: SM3 secure hash 864 instructions, as ratified in commit 56ed795 ("Update 865 riscv-crypto-spec-vector.adoc") of riscv-crypto. 866 867 - const: zvkt 868 description: 869 The standard Zvkt extension for vector data-independent execution 870 latency, as ratified in commit 56ed795 ("Update 871 riscv-crypto-spec-vector.adoc") of riscv-crypto. 872 873 # vendor extensions, each extension sorted alphanumerically under the 874 # vendor they belong to. Vendors are sorted alphanumerically as well. 875 876 # Andes 877 - const: xandespmu 878 description: 879 The Andes Technology performance monitor extension for counter overflow 880 and privilege mode filtering. For more details, see Counter Related 881 Registers in the AX45MP datasheet. 882 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 883 884 # MIPS 885 - const: xmipsexectl 886 description: 887 The MIPS extension for execution control as documented in 888 https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf 889 890 # SiFive 891 - const: xsfcease 892 description: 893 SiFive CEASE Instruction Extensions Specification. 894 See more details in 895 https://www.sifive.com/document-file/freedom-u740-c000-manual 896 897 - const: xsfcflushdlone 898 description: 899 SiFive L1D Cache Flush Instruction Extensions Specification. 900 See more details in 901 https://www.sifive.com/document-file/freedom-u740-c000-manual 902 903 - const: xsfpgflushdlone 904 description: 905 SiFive PGFLUSH Instruction Extensions for the power management. The 906 CPU will flush the L1D and enter the cease state after executing 907 the instruction. 908 909 - const: xsfvqmaccdod 910 description: 911 SiFive Int8 Matrix Multiplication Extensions Specification. 912 See more details in 913 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 914 915 - const: xsfvqmaccqoq 916 description: 917 SiFive Int8 Matrix Multiplication Extensions Specification. 918 See more details in 919 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 920 921 - const: xsfvfnrclipxfqf 922 description: 923 SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. 924 See more details in 925 https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions 926 927 - const: xsfvfwmaccqqq 928 description: 929 SiFive Matrix Multiply Accumulate Instruction Extensions Specification. 930 See more details in 931 https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction 932 933 # T-HEAD 934 - const: xtheadvector 935 description: 936 The T-HEAD specific 0.7.1 vector implementation as written in 937 https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. 938 939 allOf: 940 - if: 941 contains: 942 const: d 943 then: 944 contains: 945 const: f 946 # B comprises Zba, Zbb, and Zbs 947 - if: 948 contains: 949 const: b 950 then: 951 allOf: 952 - contains: 953 const: zba 954 - contains: 955 const: zbb 956 - contains: 957 const: zbs 958 # Zba, Zbb, Zbs together require B 959 - if: 960 allOf: 961 - contains: 962 const: zba 963 - contains: 964 const: zbb 965 - contains: 966 const: zbs 967 then: 968 contains: 969 const: b 970 # Supm depends on Smnpm or Ssnpm 971 - if: 972 contains: 973 const: supm 974 then: 975 oneOf: 976 - contains: 977 const: smnpm 978 - contains: 979 const: ssnpm 980 # Za64rs and Ziccrse depend on Zalrsc or A 981 - if: 982 contains: 983 anyOf: 984 - const: za64rs 985 - const: ziccrse 986 then: 987 oneOf: 988 - contains: 989 const: zalrsc 990 - contains: 991 const: a 992 # Zcb depends on Zca 993 - if: 994 contains: 995 const: zcb 996 then: 997 contains: 998 const: zca 999 # Zcd depends on Zca and D 1000 - if: 1001 contains: 1002 const: zcd 1003 then: 1004 allOf: 1005 - contains: 1006 const: zca 1007 - contains: 1008 const: d 1009 # Zcf depends on Zca and F 1010 - if: 1011 contains: 1012 const: zcf 1013 then: 1014 allOf: 1015 - contains: 1016 const: zca 1017 - contains: 1018 const: f 1019 # Zcmop depends on Zca 1020 - if: 1021 contains: 1022 const: zcmop 1023 then: 1024 contains: 1025 const: zca 1026 # Zfbfmin depends on F 1027 - if: 1028 contains: 1029 const: zfbfmin 1030 then: 1031 contains: 1032 const: f 1033 # Ziccamoa depends on Zaamo or A 1034 - if: 1035 contains: 1036 const: ziccamoa 1037 then: 1038 oneOf: 1039 - contains: 1040 const: zaamo 1041 - contains: 1042 const: a 1043 # Zvfbfmin depends on V or Zve32f 1044 - if: 1045 contains: 1046 const: zvfbfmin 1047 then: 1048 oneOf: 1049 - contains: 1050 const: v 1051 - contains: 1052 const: zve32f 1053 # Zvfbfwma depends on Zfbfmin and Zvfbfmin 1054 - if: 1055 contains: 1056 const: zvfbfwma 1057 then: 1058 allOf: 1059 - contains: 1060 const: zfbfmin 1061 - contains: 1062 const: zvfbfmin 1063 # Zacas depends on Zaamo 1064 - if: 1065 contains: 1066 const: zacas 1067 then: 1068 contains: 1069 const: zaamo 1070 1071 - if: 1072 contains: 1073 const: zve32x 1074 then: 1075 contains: 1076 const: zicsr 1077 1078 - if: 1079 contains: 1080 const: zve32f 1081 then: 1082 allOf: 1083 - contains: 1084 const: f 1085 - contains: 1086 const: zve32x 1087 1088 - if: 1089 contains: 1090 const: zve64x 1091 then: 1092 contains: 1093 const: zve32x 1094 1095 - if: 1096 contains: 1097 const: zve64f 1098 then: 1099 allOf: 1100 - contains: 1101 const: f 1102 - contains: 1103 const: zve32f 1104 - contains: 1105 const: zve64x 1106 1107 - if: 1108 contains: 1109 const: zve64d 1110 then: 1111 allOf: 1112 - contains: 1113 const: d 1114 - contains: 1115 const: zve64f 1116 1117 - if: 1118 contains: 1119 anyOf: 1120 - const: zvbc 1121 - const: zvkn 1122 - const: zvknc 1123 - const: zvkng 1124 - const: zvknhb 1125 - const: zvksc 1126 then: 1127 contains: 1128 anyOf: 1129 - const: v 1130 - const: zve64x 1131 1132 - if: 1133 contains: 1134 anyOf: 1135 - const: zvbb 1136 - const: zvkb 1137 - const: zvkg 1138 - const: zvkned 1139 - const: zvknha 1140 - const: zvksed 1141 - const: zvksh 1142 - const: zvks 1143 - const: zvkt 1144 then: 1145 contains: 1146 anyOf: 1147 - const: v 1148 - const: zve32x 1149 # Zclsd depends on Zilsd and Zca 1150 - if: 1151 contains: 1152 anyOf: 1153 - const: zclsd 1154 then: 1155 contains: 1156 allOf: 1157 - const: zilsd 1158 - const: zca 1159 # Smcdeleg depends on Sscsrind, Zihpm, Zicntr 1160 - if: 1161 contains: 1162 const: smcdeleg 1163 then: 1164 allOf: 1165 - contains: 1166 const: sscsrind 1167 - contains: 1168 const: zihpm 1169 - contains: 1170 const: zicntr 1171 # Ssccfg depends on Smcdeleg, Sscsrind, Zihpm, Zicntr 1172 - if: 1173 contains: 1174 const: ssccfg 1175 then: 1176 allOf: 1177 - contains: 1178 const: smcdeleg 1179 - contains: 1180 const: sscsrind 1181 - contains: 1182 const: zihpm 1183 - contains: 1184 const: zicntr 1185 1186allOf: 1187 # Zcf extension does not exist on rv64 1188 - if: 1189 properties: 1190 riscv,isa-extensions: 1191 contains: 1192 const: zcf 1193 riscv,isa-base: 1194 contains: 1195 const: rv64i 1196 then: 1197 properties: 1198 riscv,isa-extensions: 1199 not: 1200 contains: 1201 const: zcf 1202 # Zilsd extension does not exist on rv64 1203 - if: 1204 properties: 1205 riscv,isa-base: 1206 contains: 1207 const: rv64i 1208 then: 1209 properties: 1210 riscv,isa-extensions: 1211 not: 1212 contains: 1213 const: zilsd 1214 1215additionalProperties: true 1216... 1217