1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC 4 * 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 6 */ 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 compatible = "wm,wm8850"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "arm,cortex-a9"; 20 reg = <0x0>; 21 next-level-cache = <&l2_cache>; 22 }; 23 }; 24 25 aliases { 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &uart2; 29 serial3 = &uart3; 30 }; 31 32 soc { 33 #address-cells = <1>; 34 #size-cells = <1>; 35 compatible = "simple-bus"; 36 ranges; 37 interrupt-parent = <&intc0>; 38 39 intc0: interrupt-controller@d8140000 { 40 compatible = "via,vt8500-intc"; 41 interrupt-controller; 42 reg = <0xd8140000 0x10000>; 43 #interrupt-cells = <1>; 44 }; 45 46 /* Secondary IC cascaded to intc0 */ 47 intc1: interrupt-controller@d8150000 { 48 compatible = "via,vt8500-intc"; 49 interrupt-controller; 50 #interrupt-cells = <1>; 51 reg = <0xD8150000 0x10000>; 52 interrupts = <56 57 58 59 60 61 62 63>; 53 }; 54 55 pinctrl: pinctrl@d8110000 { 56 compatible = "wm,wm8850-pinctrl"; 57 reg = <0xd8110000 0x10000>; 58 interrupt-controller; 59 #interrupt-cells = <2>; 60 gpio-controller; 61 #gpio-cells = <2>; 62 }; 63 64 chipid@d8120000 { 65 compatible = "via,vt8500-scc-id"; 66 reg = <0xd8120000 0x4>; 67 }; 68 69 pmc@d8130000 { 70 compatible = "via,vt8500-pmc"; 71 reg = <0xd8130000 0x1000>; 72 73 clocks { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 ref25: ref25M { 78 #clock-cells = <0>; 79 compatible = "fixed-clock"; 80 clock-frequency = <25000000>; 81 }; 82 83 ref24: ref24M { 84 #clock-cells = <0>; 85 compatible = "fixed-clock"; 86 clock-frequency = <24000000>; 87 }; 88 89 plla: plla { 90 #clock-cells = <0>; 91 compatible = "wm,wm8850-pll-clock"; 92 clocks = <&ref24>; 93 reg = <0x200>; 94 }; 95 96 pllb: pllb { 97 #clock-cells = <0>; 98 compatible = "wm,wm8850-pll-clock"; 99 clocks = <&ref24>; 100 reg = <0x204>; 101 }; 102 103 pllc: pllc { 104 #clock-cells = <0>; 105 compatible = "wm,wm8850-pll-clock"; 106 clocks = <&ref24>; 107 reg = <0x208>; 108 }; 109 110 plld: plld { 111 #clock-cells = <0>; 112 compatible = "wm,wm8850-pll-clock"; 113 clocks = <&ref24>; 114 reg = <0x20c>; 115 }; 116 117 plle: plle { 118 #clock-cells = <0>; 119 compatible = "wm,wm8850-pll-clock"; 120 clocks = <&ref24>; 121 reg = <0x210>; 122 }; 123 124 pllf: pllf { 125 #clock-cells = <0>; 126 compatible = "wm,wm8850-pll-clock"; 127 clocks = <&ref24>; 128 reg = <0x214>; 129 }; 130 131 pllg: pllg { 132 #clock-cells = <0>; 133 compatible = "wm,wm8850-pll-clock"; 134 clocks = <&ref24>; 135 reg = <0x218>; 136 }; 137 138 clkarm: arm { 139 #clock-cells = <0>; 140 compatible = "via,vt8500-device-clock"; 141 clocks = <&plla>; 142 divisor-reg = <0x300>; 143 }; 144 145 clkahb: ahb { 146 #clock-cells = <0>; 147 compatible = "via,vt8500-device-clock"; 148 clocks = <&pllb>; 149 divisor-reg = <0x304>; 150 }; 151 152 clkapb: apb { 153 #clock-cells = <0>; 154 compatible = "via,vt8500-device-clock"; 155 clocks = <&pllb>; 156 divisor-reg = <0x320>; 157 }; 158 159 clkddr: ddr { 160 #clock-cells = <0>; 161 compatible = "via,vt8500-device-clock"; 162 clocks = <&plld>; 163 divisor-reg = <0x310>; 164 }; 165 166 clkuart0: uart0 { 167 #clock-cells = <0>; 168 compatible = "via,vt8500-device-clock"; 169 clocks = <&ref24>; 170 enable-reg = <0x254>; 171 enable-bit = <24>; 172 }; 173 174 clkuart1: uart1 { 175 #clock-cells = <0>; 176 compatible = "via,vt8500-device-clock"; 177 clocks = <&ref24>; 178 enable-reg = <0x254>; 179 enable-bit = <25>; 180 }; 181 182 clkuart2: uart2 { 183 #clock-cells = <0>; 184 compatible = "via,vt8500-device-clock"; 185 clocks = <&ref24>; 186 enable-reg = <0x254>; 187 enable-bit = <26>; 188 }; 189 190 clkuart3: uart3 { 191 #clock-cells = <0>; 192 compatible = "via,vt8500-device-clock"; 193 clocks = <&ref24>; 194 enable-reg = <0x254>; 195 enable-bit = <27>; 196 }; 197 198 clkpwm: pwm { 199 #clock-cells = <0>; 200 compatible = "via,vt8500-device-clock"; 201 clocks = <&pllb>; 202 divisor-reg = <0x350>; 203 enable-reg = <0x250>; 204 enable-bit = <17>; 205 }; 206 207 clksdhc: sdhc { 208 #clock-cells = <0>; 209 compatible = "via,vt8500-device-clock"; 210 clocks = <&pllb>; 211 divisor-reg = <0x330>; 212 divisor-mask = <0x3f>; 213 enable-reg = <0x250>; 214 enable-bit = <0>; 215 }; 216 }; 217 }; 218 219 fb: fb@d8051700 { 220 compatible = "wm,wm8505-fb"; 221 reg = <0xd8051700 0x200>; 222 }; 223 224 ge_rops@d8050400 { 225 compatible = "wm,prizm-ge-rops"; 226 reg = <0xd8050400 0x100>; 227 }; 228 229 pwm: pwm@d8220000 { 230 #pwm-cells = <3>; 231 compatible = "via,vt8500-pwm"; 232 reg = <0xd8220000 0x100>; 233 clocks = <&clkpwm>; 234 }; 235 236 timer@d8130100 { 237 compatible = "via,vt8500-timer"; 238 reg = <0xd8130100 0x28>; 239 interrupts = <36>, <37>, <38>, <39>; 240 }; 241 242 usb@d8007900 { 243 compatible = "via,vt8500-ehci"; 244 reg = <0xd8007900 0x200>; 245 interrupts = <26>; 246 }; 247 248 usb@d8007b00 { 249 compatible = "platform-uhci"; 250 reg = <0xd8007b00 0x200>; 251 interrupts = <26>; 252 }; 253 254 usb@d8008d00 { 255 compatible = "platform-uhci"; 256 reg = <0xd8008d00 0x200>; 257 interrupts = <26>; 258 }; 259 260 uart0: serial@d8200000 { 261 compatible = "via,vt8500-uart"; 262 reg = <0xd8200000 0x1040>; 263 interrupts = <32>; 264 clocks = <&clkuart0>; 265 status = "disabled"; 266 }; 267 268 uart1: serial@d82b0000 { 269 compatible = "via,vt8500-uart"; 270 reg = <0xd82b0000 0x1040>; 271 interrupts = <33>; 272 clocks = <&clkuart1>; 273 status = "disabled"; 274 }; 275 276 uart2: serial@d8210000 { 277 compatible = "via,vt8500-uart"; 278 reg = <0xd8210000 0x1040>; 279 interrupts = <47>; 280 clocks = <&clkuart2>; 281 status = "disabled"; 282 }; 283 284 uart3: serial@d82c0000 { 285 compatible = "via,vt8500-uart"; 286 reg = <0xd82c0000 0x1040>; 287 interrupts = <50>; 288 clocks = <&clkuart3>; 289 status = "disabled"; 290 }; 291 292 rtc@d8100000 { 293 compatible = "via,vt8500-rtc"; 294 reg = <0xd8100000 0x10000>; 295 interrupts = <48>; 296 }; 297 298 mmc@d800a000 { 299 compatible = "wm,wm8505-sdhc"; 300 reg = <0xd800a000 0x1000>; 301 interrupts = <20 21>; 302 clocks = <&clksdhc>; 303 bus-width = <4>; 304 sdon-inverted; 305 }; 306 307 ethernet@d8004000 { 308 compatible = "via,vt8500-rhine"; 309 reg = <0xd8004000 0x100>; 310 interrupts = <10>; 311 }; 312 313 l2_cache: cache-controller@d9000000 { 314 compatible = "arm,pl310-cache"; 315 reg = <0xd9000000 0x1000>; 316 arm,double-linefill = <1>; 317 arm,dynamic-clock-gating = <1>; 318 arm,shared-override; 319 arm,standby-mode = <1>; 320 cache-level = <2>; 321 cache-unified; 322 prefetch-data = <1>; 323 prefetch-instr = <1>; 324 }; 325 }; 326}; 327