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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP10InstrResources.td13 // 22 Cycles Binary Floating Point operations, 2 input operands
21 // 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands
27 // 24 Cycles Binary Floating Point operations, 2 input operands
33 // 26 Cycles Binary Floating Point operations, 1 input operands
41 // 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands
47 // 27 Cycles Binary Floating Point operations, 1 input operands
53 // 27 Cycles Binary Floating Point operations, 2 input operands
62 // 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands
68 // 36 Cycles Binary Floating Point operations, 1 input operands
77 // 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands
[all …]
H A DPPCScheduleP10.td83 // A BF pipeline may take from 7 to 36 cycles to complete.
84 // Some BF operations may keep the pipeline busy for up to 10 cycles.
114 // A BR pipeline may take 2 cycles to complete.
119 // A CY pipeline may take 7 cycles to complete.
124 // A DF pipeline may take from 13 to 174 cycles to complete.
125 // Some DF operations may keep the pipeline busy for up to 67 cycles.
210 // A DV pipeline may take from 20 to 83 cycles to complete.
211 // Some DV operations may keep the pipeline busy for up to 33 cycles.
262 // A DX pipeline may take 5 cycles to complete.
267 // A F2 pipeline may take 4 cycles t
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/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A Dother.json5 "BriefDescription": "Cycles where the Micro-Op Queue is empty."
22 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T…
28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T…
34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T…
40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T…
46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t…
52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T…
58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T…
64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T…
70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t…
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.txt34 FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
77 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
82 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
86 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
88 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
99 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
101 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp42 // Cycles - Number of cycles until return if HasReturn is true, otherwise
43 // number of cycles until end of the BB
44 unsigned int Cycles = 0; member
47 VisitedBBInfo(bool HasReturn, unsigned int Cycles) in VisitedBBInfo()
48 : HasReturn(HasReturn), Cycles(Cycles) {} in VisitedBBInfo()
75 unsigned int Cycles = 0);
78 unsigned int &Cycles);
87 // cycles until the return, starting from the entry block.
133 unsigned Cycles = ReturnBB.second; in runOnMachineFunction() local
140 if (Cycles < Threshold) { in runOnMachineFunction()
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A Dpipeline.json345 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
356 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
361 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt…
375 "BriefDescription": "Reference cycles when the core is not in halt state.",
379 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h…
384 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
389 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
395 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
400 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt…
405 "BriefDescription": "Core cycles when the thread is not in halt state.",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A Dpipeline.json345 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
356 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
361 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt…
375 "BriefDescription": "Reference cycles when the core is not in halt state.",
379 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h…
384 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
389 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
395 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
400 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt…
405 "BriefDescription": "Core cycles when the thread is not in halt state.",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A Dcrypto.json11 "BriefDescription": "PRNG Cycles",
12 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing P…
23 "BriefDescription": "PRNG Blocked Cycles",
24 …"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU …
35 "BriefDescription": "SHA Cycles",
36 …"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the S…
47 "BriefDescription": "SHA Bloced Cycles",
48 …"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU b…
59 "BriefDescription": "DEA Cycles",
60 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A Dcrypto.json11 "BriefDescription": "PRNG Cycles",
12 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing P…
23 "BriefDescription": "PRNG Blocked Cycles",
24 …"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU …
35 "BriefDescription": "SHA Cycles",
36 …"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the S…
47 "BriefDescription": "SHA Bloced Cycles",
48 …"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU b…
59 "BriefDescription": "DEA Cycles",
60 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A Dcrypto.json11 "BriefDescription": "PRNG Cycles",
12 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing P…
23 "BriefDescription": "PRNG Blocked Cycles",
24 …"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU …
35 "BriefDescription": "SHA Cycles",
36 …"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the S…
47 "BriefDescription": "SHA Bloced Cycles",
48 …"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU b…
59 "BriefDescription": "DEA Cycles",
60 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A Dcrypto.json11 "BriefDescription": "PRNG Cycles",
12 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing P…
23 "BriefDescription": "PRNG Blocked Cycles",
24 …"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU …
35 "BriefDescription": "SHA Cycles",
36 …"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the S…
47 "BriefDescription": "SHA Bloced Cycles",
48 …"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU b…
59 "BriefDescription": "DEA Cycles",
60 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A Dcrypto.json11 "BriefDescription": "PRNG Cycles",
12 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing P…
23 "BriefDescription": "PRNG Blocked Cycles",
24 …"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU …
35 "BriefDescription": "SHA Cycles",
36 …"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the S…
47 "BriefDescription": "SHA Bloced Cycles",
48 …"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU b…
59 "BriefDescription": "DEA Cycles",
60 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylake/
H A Dfrontend.json18 …er (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28cycles. These cycles do not include uops routed through because of the switch itself, for example,…
115 …er an interval where the front-end delivered no uops for a period of 128 cycles which was not inte…
128 …ter an interval where the front-end delivered no uops for a period of 16 cycles which was not inte…
136 …hat are delivered to the back-end after a front-end stall of at least 16 cycles. During this perio…
142 …fter an interval where the front-end delivered no uops for a period of 2 cycles which was not inte…
155 …er an interval where the front-end delivered no uops for a period of 256 cycles which was not inte…
168 …nterval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not inte…
176 …ack-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is …
[all …]
H A Dpipeline.json3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A…
169 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i…
178 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
188 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un…
197 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i…
206 "BriefDescription": "Reference cycles when the core is not in halt state.",
210 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. …
215 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
225 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un…
245 "BriefDescription": "Core cycles when the thread is not in halt state",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A Dfrontend.json18 …er (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28cycles. These cycles do not include uops routed through because of the switch itself, for example,…
115 …er an interval where the front-end delivered no uops for a period of 128 cycles which was not inte…
128 …ter an interval where the front-end delivered no uops for a period of 16 cycles which was not inte…
136 …hat are delivered to the back-end after a front-end stall of at least 16 cycles. During this perio…
142 …fter an interval where the front-end delivered no uops for a period of 2 cycles which was not inte…
155 …er an interval where the front-end delivered no uops for a period of 256 cycles which was not inte…
168 …nterval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not inte…
176 …ack-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is …
[all …]
H A Dpipeline.json3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A…
169 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i…
178 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
188 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un…
197 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i…
206 "BriefDescription": "Reference cycles when the core is not in halt state.",
210 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. …
215 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
225 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un…
245 "BriefDescription": "Core cycles when the thread is not in halt state",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A Dfrontend.json18 …er (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28cycles. These cycles do not include uops routed through because of the switch itself, for example,…
115 …er an interval where the front-end delivered no uops for a period of 128 cycles which was not inte…
128 …ter an interval where the front-end delivered no uops for a period of 16 cycles which was not inte…
136 …hat are delivered to the back-end after a front-end stall of at least 16 cycles. During this perio…
142 …fter an interval where the front-end delivered no uops for a period of 2 cycles which was not inte…
155 …er an interval where the front-end delivered no uops for a period of 256 cycles which was not inte…
168 …nterval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not inte…
176 …ack-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is …
[all …]
H A Dpipeline.json3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A…
169 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i…
178 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
188 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un…
197 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i…
206 "BriefDescription": "Reference cycles when the core is not in halt state.",
210 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. …
215 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
225 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un…
245 "BriefDescription": "Core cycles when the thread is not in halt state",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A Dfrontend.json23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
28 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
33 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre…
53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB…
58 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL…
73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
79 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
90 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
95 "BriefDescription": "Cycles MITE is delivering 4 Uops",
[all …]
H A Dpipeline.json15 "BriefDescription": "Cycles when divider is busy executing divide operations",
20 …"PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=…
371 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
382 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
400 "BriefDescription": "Reference cycles when the core is not in halt state.",
408 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
413 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
419 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
428 "BriefDescription": "Core cycles when the thread is not in halt state.",
437 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Dfrontend.json23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
28 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
33 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre…
53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB…
58 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL…
73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
79 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
90 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
95 "BriefDescription": "Cycles MITE is delivering 4 Uops",
[all …]
H A Dpipeline.json15 "BriefDescription": "Cycles when divider is busy executing divide operations",
20 …"PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=…
371 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
382 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
400 "BriefDescription": "Reference cycles when the core is not in halt state.",
408 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
413 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
419 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
428 "BriefDescription": "Core cycles when the thread is not in halt state.",
437 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/
H A Dpipeline.json3 "BriefDescription": "Cycles when divider is busy executing divide operations",
381 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
392 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
410 "BriefDescription": "Reference cycles when the core is not in halt state.",
414 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h…
419 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
424 … "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
430 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
439 "BriefDescription": "Core cycles when the thread is not in halt state",
443 …"PublicDescription": "This event counts the number of core cycles while the thread is not in a hal…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/
H A Dpipeline.json3 "BriefDescription": "Cycles when divider is busy executing divide operations",
381 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
392 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
410 "BriefDescription": "Reference cycles when the core is not in halt state.",
414 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h…
419 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
424 … "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
430 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
439 "BriefDescription": "Core cycles when the thread is not in halt state",
443 …"PublicDescription": "This event counts the number of core cycles while the thread is not in a hal…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwell/
H A Dpipeline.json3 "BriefDescription": "Cycles when divider is busy executing divide operations",
381 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
392 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
410 "BriefDescription": "Reference cycles when the core is not in halt state.",
414 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h…
419 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
424 … "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
430 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
439 "BriefDescription": "Core cycles when the thread is not in halt state",
443 …"PublicDescription": "This event counts the number of core cycles while the thread is not in a hal…
[all …]

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