| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | GenericUniformityImpl.h | 1 //===- GenericUniformityImpl.h -----------------------*- C++ -*------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 // - UniformityAnalysis.cpp
23 //===----------------------------------------------------------------------===//
30 /// divergence (whose discovery must be implemented by a CFG- or even
31 /// target-specific derived class), divergence of values is propagated from
32 /// definition to uses in a straight-forward way. The main complexity lies in
42 //===----------------------------------------------------------------------===//
60 /// Construct a specially modified post-order traversal of cycles.
[all …]
|
| H A D | GenericCycleImpl.h | 1 //===- GenericCycleImpl.h -------------------------------------*- C++ -*---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
18 /// - llvm/lib/IR/CycleInfo.cpp
19 /// - llvm/lib/CodeGen/MachineCycleAnalysis.cpp
21 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "generic-cycle-impl"
39 if (Depth > C->Depth) in contains()
41 while (Depth < C->Depth) in contains()
42 C = C->ParentCycle; in contains()
[all …]
|
| H A D | GenericCycleInfo.h | 1 //===- GenericCycleInfo.h - Info for Cycles in any IR ------*- C++ -*------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// \brief Find all cycles in a control-flow graph, including irreducible loops.
15 /// - A cycle is a generalization of a loop which can represent
17 /// - Cycles identified in a program are implementation defined,
19 /// - Cycles are well-nested, and form a forest with a parent-child
21 /// - In any choice of DFS, every natural loop L is represented by a
22 /// unique cycle C which is a superset of L.
23 /// - In the absence of irreducible control flow, the cycles are
[all …]
|
| /freebsd/usr.bin/gprof/ |
| H A D | arcs.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
10 * 1. Redistributions of source code must retain the above copyright
56 count , parentp -> name , childp -> name ); in addarc()
67 arcp -> arc_count , count ); in addarc()
70 arcp -> arc_count += count; in addarc()
73 arcp = (arctype *)calloc( 1 , sizeof *arcp ); in addarc()
75 errx( 1 , "malloc failed" ); in addarc()
76 arcp -> arc_parentp = parentp; in addarc()
77 arcp -> arc_childp = childp; in addarc()
[all …]
|
| H A D | gprof.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
10 * 1. Redistributions of source code must retain the above copyright
53 #define TRUE 1
58 * scaling and makes bucket:pc densities of more than 1/2 useless.
93 struct arcstruct *arc_parentlist; /* parents-of-this-child list */
94 struct arcstruct *arc_childlist; /* children-of-this-parent list */
95 struct arcstruct *arc_next; /* list of arcs on cycle */
127 int toporder; /* graph call chain top-sort order */
128 int cycleno; /* internal number of cycle on */
[all …]
|
| /freebsd/contrib/bmake/unit-tests/ |
| H A D | dotwait.mk | 5 TESTS= simple recursive shared cycle
6 PAUSE= sleep 1
11 # Ignore "--- target ---" lines printed by parallel make.
14 @${.MAKE} -f ${THISMAKEFILE} -j4 $t 2>&1 | grep -v "^--- "
18 # Within each test, the names of the sub-targets follow these
34 PARALLEL_TARG= ${.TARGET:C/\.[a-z]/.*/g:Q}
41 simple: simple.1 .WAIT simple.2
56 # cycle: the cyclic dependency must not cause infinite recursion
58 cycle: cycle.1.99 .WAIT cycle.2.99
59 cycle.2.99: cycle.2.98 _ECHOUSE
[all …]
|
| /freebsd/share/doc/psd/18.gprof/ |
| H A D | postp.me | 7 .\" 1. Redistributions of source code must retain the above copyright
32 .sh 1 "Post Processing"
47 An example is given in Figure 1.
59 Figure 1.
88 In these cases, we discover strongly-connected
92 We use a variation of Tarjan's strongly-connected
94 that discovers strongly-connected components as it is assigning
99 For example, a self-recursive routine
100 (a trivial cycle in the call graph)
109 Time is not propagated from one member of a cycle to another,
[all …]
|
| H A D | present.me | 7 .\" 1. Redistributions of source code must retain the above copyright
28 .sh 1 "Data Presentation"
69 0.20 1.20 4/10 \ \ \s-1CALLER1\s+1 [7]
70 0.30 1.80 6/10 \ \ \s-1CALLER2\s+1 [1]
71 [2] 41.5 0.50 3.00 10+4 \s-1EXAMPLE\s+1 [2]
72 1.50 1.00 20/40 \ \ \s-1SUB1\s+1 <cycle1> [4]
73 0.00 0.50 1/5 \ \ \s-1SUB2\s+1 [9]
74 0.00 0.00 0/5 \ \ \s-1SUB3\s+1 [11]
77 Profile entry for \s-1EXAMPLE\s+1.
82 but we are limited by the two-dimensional nature of our output
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ScoreboardHazardRecognizer.cpp | 1 //===- ScoreboardHazardRecognizer.cpp - Scheduler Support -----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // encapsultes hazard-avoidance heuristics for scheduling, based on the
13 //===----------------------------------------------------------------------===//
18 #include "llvm/Config/llvm-config.h"
36 // the scoreboard. We always make the scoreboard at least 1 cycle deep to in ScoreboardHazardRecognizer()
38 unsigned ScoreboardDepth = 1; in ScoreboardHazardRecognizer()
39 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
41 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 1 //===- ModuloSchedule.h - Software pipeline schedule expansion ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
18 // A schedule is, for every instruction in a block, a Cycle and a Stage. Note
19 // that we only support single-block loops, so "block" and "loop" can be used
22 // The Cycle of an instruction defines a partial order of the instructions in
23 // the remapped loop. Instructions within a cycle must not consume the output
24 // of any instruction in the same cycle. Cycle information is assumed to have
26 // lock-step (for example in a VLIW ISA).
33 // I1[0], I0[1] Execute I0 of iteration 1 and I1 of iteration 1
[all …]
|
| H A D | ScoreboardHazardRecognizer.h | 1 //=- llvm/CodeGen/ScoreboardHazardRecognizer.h - Schedule Support -*- C++ -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // encapsulates hazard-avoidance heuristics for scheduling, based on the
13 //===----------------------------------------------------------------------===//
31 // mask of the FUs in use in the cycle currently being
32 // schedule. Scoreboard[1] is a mask for the next cycle. The
33 // Scoreboard is used as a circular buffer with the current cycle
37 // bottom-up scheduler, then the scoreboard cycles are the inverse of the
47 // Indices into the Scoreboard that represent the current cycle.
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/ |
| H A D | floating-point.json | 5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/ |
| H A D | basic.json | 6 "PublicDescription": "Cycle Count"
9 "EventCode": "1",
18 "PublicDescription": "Level-1 I-Cache Directory Write Count"
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
30 "PublicDescription": "Level-1 D-Cache Directory Write Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41 "BriefDescription": "Problem-State CPU Cycles",
42 "PublicDescription": "Problem-State Cycle Count"
47 "BriefDescription": "Problem-State Instructions",
48 "PublicDescription": "Problem-State Instruction Count"
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/ |
| H A D | basic.json | 6 "PublicDescription": "Cycle Count"
9 "EventCode": "1",
18 "PublicDescription": "Level-1 I-Cache Directory Write Count"
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
30 "PublicDescription": "Level-1 D-Cache Directory Write Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41 "BriefDescription": "Problem-State CPU Cycles",
42 "PublicDescription": "Problem-State Cycle Count"
47 "BriefDescription": "Problem-State Instructions",
48 "PublicDescription": "Problem-State Instruction Count"
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/ |
| H A D | basic.json | 6 "PublicDescription": "Cycle Count"
9 "EventCode": "1",
18 "PublicDescription": "Level-1 I-Cache Directory Write Count"
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
30 "PublicDescription": "Level-1 D-Cache Directory Write Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41 "BriefDescription": "Problem-State CPU Cycles",
42 "PublicDescription": "Problem-State Cycle Count"
47 "BriefDescription": "Problem-State Instructions",
48 "PublicDescription": "Problem-State Instruction Count"
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/ |
| H A D | basic.json | 6 "PublicDescription": "Cycle Count"
9 "EventCode": "1",
18 "PublicDescription": "Level-1 I-Cache Directory Write Count"
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
30 "PublicDescription": "Level-1 D-Cache Directory Write Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41 "BriefDescription": "Problem-State CPU Cycles",
42 "PublicDescription": "Problem-State Cycle Count"
47 "BriefDescription": "Problem-State Instructions",
48 "PublicDescription": "Problem-State Instruction Count"
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/ |
| H A D | floating-point.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
6 "CounterMask": "1",
15 "Counter": "0,1,2,3",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/ |
| H A D | floating-point.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
6 "CounterMask": "1",
15 "Counter": "0,1,2,3",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/ |
| H A D | floating-point.json | 6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
26 "BriefDescription": "Total number uOps assigned to pipe 1.",
27 …- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric o…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num…
52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | pwm-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 1 //===- P9InstrResources.td - P9 Instruction Resource Defs -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // - Each CPU is made up of two superslices.
17 // - Each superslice is made up of two slices. Therefore, there are 4 slices
19 // - Up to 6 instructions can be dispatched to each CPU. Three per superslice.
20 // - Each CPU has:
21 // - One CY (Crypto) unit P9_CY_*
22 // - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
23 // - Two PM (Permute) units. One on each superslice. P9_PM_*
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | renesas,sh-msiof.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | pwm-vibrator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
23 const: pwm-vibrator
25 pwm-names:
[all …]
|
| /freebsd/share/doc/papers/kerntune/ |
| H A D | 2.t | 8 .\" 1. Redistributions of source code must retain the above copyright
78 but we are limited by the two-dimensional nature of our output
91 Figure 1 shows a sample \fIgprof\fP entry.
104 0.20 1.20 4/10 \ \ \s-1CALLER1\s+1 [7]
105 0.30 1.80 6/10 \ \ \s-1CALLER2\s+1 [1]
106 [2] 41.5 0.50 3.00 10+4 \s-1EXAMPLE\s+1 [2]
107 1.50 1.00 20/40 \ \ \s-1SUB1\s+1 <cycle1> [4]
108 0.00 0.50 1/5 \ \ \s-1SUB2\s+1 [9]
109 0.00 0.00 0/5 \ \ \s-1SUB3\s+1 [11]
112 Figure 1. Profile entry for \s-1EXAMPLE\s+1.
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/ |
| H A D | pipeline.json | 5 "Counter": "0,1,2,3",
8 "PEBS": "1",
9 "PEBScounters": "0,1,2,3",
16 "Counter": "0,1,2,3",
19 "PEBS": "1",
20 "PEBScounters": "0,1,2,3",
27 "Counter": "0,1,2,3",
30 "PEBS": "1",
31 "PEBScounters": "0,1,2,3",
38 "Counter": "0,1,2,3",
[all …]
|