Lines Matching +full:cycle +full:- +full:1
1 //===- P9InstrResources.td - P9 Instruction Resource Defs -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // - Each CPU is made up of two superslices.
17 // - Each superslice is made up of two slices. Therefore, there are 4 slices
19 // - Up to 6 instructions can be dispatched to each CPU. Three per superslice.
20 // - Each CPU has:
21 // - One CY (Crypto) unit P9_CY_*
22 // - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
23 // - Two PM (Permute) units. One on each superslice. P9_PM_*
24 // - Two DIV (Fixed Point Divide) units. One on each superslize. P9_DIV_*
25 // - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_*
26 // - Four DP (Floating Point) units. One on each slice. P9_DP_*
28 // - Four AGEN (Address Generation) units. One for each slice. P9_AGEN_*
29 // - Four Load/Store Queues. P9_LS_*
30 // - Each set of instructions will require a number of these resources.
31 //===----------------------------------------------------------------------===//
33 // Two cycle ALU vector operation that uses an entire superslice.
35 // (EXECE, EXECO) and 1 dispatch (DISP) to the given superslice.
92 (instregex "MTFSB(0|1)$"),
205 // Three cycle ALU vector operation that uses an entire superslice.
207 // (EXECE, EXECO) and 1 dispatch (DISP) to the given superslice.
290 // 7 cycle DP vector operation that uses an entire superslice.
401 // 5 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
409 // 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
452 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
461 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
468 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
488 // 7 cycle DP operation. One DP unit, one EXEC pipeline and 1 dispatch units.
524 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
634 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
658 // 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
666 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
683 // 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
691 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
700 // 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
709 // 6 Cycle Load uses a single slice.
715 // 5 Cycle Load uses a single slice.
734 // 4 Cycle Load uses a single slice.
762 // 4 Cycle Restricted load uses a single slice but the dispatch for the whole
870 // Cracked 3-Way Load Instruction
882 // both EXECE, EXECO pipelines as well as 1 dispatch for the PM. The Load
883 // requires the remaining 1 dispatch.
920 // 5 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
929 // 12 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
943 // 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
955 // 24 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
973 // 40 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
1049 // One is three cycle ALU the ohter is a two cycle ALU.
1109 // Cracked ALU instruction composed of three consecutive 2 cycle loads for a
1130 // 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1136 // 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1143 // 36 Cycle DP Instruction.
1150 // 36 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1156 // 36 Cycle DP Vector Instruction.
1163 // 27 Cycle DP Vector Instruction.
1170 // 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1177 // 26 Cycle DP Instruction.
1183 // 26 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1189 // 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1196 // 33 Cycle DP Instruction. Takes one slice and 1 dispatch.
1202 // 22 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1208 // 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
1215 // 22 Cycle DP Instruction. Takes one slice and 1 dispatch.
1221 // 24 Cycle DP Vector Instruction. Takes one full superslice.
1222 // Includes both EXECE, EXECO pipelines and 1 dispatch for the given
1230 // 33 Cycle DP Vector Instruction. Takes one full superslice.
1231 // Includes both EXECE, EXECO pipelines and 1 dispatch for the given
1284 // 6 Cycle CY operation. Only one CY unit per CPU so we use a whole
1296 // Two Cycle Branch
1329 // Five Cycle Branch with a 2 Cycle ALU Op
1398 )> { let Unsupported = 1; }
1439 )> { let Unsupported = 1; }