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/freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dother.json3 "PublicDescription": "This event counts the occurrence count of the micro-operation split.",
4 "EventCode": "0x139",
6 "BriefDescription": "This event counts the occurrence count of the micro-operation split."
9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol…
10 "EventCode": "0x180",
12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old…
15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
16 "EventCode": "0x181",
18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
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/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DGenericCycleImpl.h1 //===- GenericCycleImpl.h -------------------------------------*- C++ -*---===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
18 /// - llvm/lib/IR/CycleInfo.cpp
19 /// - llvm/lib/CodeGen/MachineCycleAnalysis.cpp
21 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "generic-cycle-impl"
39 if (Depth > C->Depth) in contains()
41 while (Depth < C->Depth) in contains()
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H A DGenericCycleInfo.h1 //===- GenericCycleInfo.h - Info for Cycles in any IR ------*- C++ -*------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// \brief Find all cycles in a control-flow graph, including irreducible loops.
15 /// - A cycle is a generalization of a loop which can represent
17 /// - Cycles identified in a program are implementation defined,
19 /// - Cycles are well-nested, and form a forest with a parent-child
21 /// - In any choice of DFS, every natural loop L is represented by a
22 /// unique cycle C which is a superset of L.
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H A DGenericUniformityImpl.h1 //===- GenericUniformityImpl.h -----------------------*- C++ -*------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 // - UniformityAnalysis.cpp
23 //===----------------------------------------------------------------------===//
30 /// divergence (whose discovery must be implemented by a CFG- or even
31 /// target-specific derived class), divergence of values is propagated from
32 /// definition to uses in a straight-forward way. The main complexity lies in
42 //===----------------------------------------------------------------------===//
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/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json9 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt…
10 "EventCode": "0xE1",
12 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt…
15 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt…
16 "EventCode": "0xE2",
18 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt…
21 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty…
22 "EventCode": "0xE3",
24 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty…
27 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal…
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/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A Dpipeline.json21 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc…
22 "EventCode": "0xE1",
24 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc…
27 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr…
28 "EventCode": "0xE2",
30 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr…
33 "PublicDescription": "No operation issued due to the frontend, pre-decode error",
34 "EventCode": "0xE3",
36 "BriefDescription": "No operation issued due to the frontend, pre-decode error"
39 …No operation issued due to the backend interlock. This event counts every cycle where the issue of…
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/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A Dfloating-point.json4 "EventCode": "0x00",
6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
7 "UMask": "0x0f"
11 "EventCode": "0x00",
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
14 "UMask": "0x08"
18 "EventCode": "0x00",
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
21 "UMask": "0x04"
25 "EventCode": "0x00",
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/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json4 "EventCode": "0x00",
5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
7 "UMask": "0xf0"
11 "EventCode": "0x00",
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
14 "UMask": "0x80"
18 "EventCode": "0x00",
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
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/freebsd/usr.bin/gprof/
H A Darcs.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
56 count , parentp -> name , childp -> name ); in addarc()
60 if ( arcp != 0 ) { in addarc()
67 arcp -> arc_count , count ); in addarc()
70 arcp -> arc_count += count; in addarc()
76 arcp -> arc_parentp = parentp; in addarc()
77 arcp -> arc_childp = childp; in addarc()
78 arcp -> arc_count = count; in addarc()
82 arcp -> arc_childlist = parentp -> children; in addarc()
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H A Dgprof.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
43 #define OFFSET_OF_CODE 0
52 #define FALSE 0
93 struct arcstruct *arc_parentlist; /* parents-of-this-child list */
94 struct arcstruct *arc_childlist; /* children-of-this-parent list */
95 struct arcstruct *arc_next; /* list of arcs on cycle */
104 #define DEADARC 0x01 /* time should not propagate across the arc */
105 #define ONLIST 0x02 /* arc is on list of arcs in cycles */
127 int toporder; /* graph call chain top-sort order */
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/freebsd/contrib/bmake/unit-tests/
H A Ddotwait.mk5 TESTS= simple recursive shared cycle
11 # Ignore "--- target ---" lines printed by parallel make.
14 @${.MAKE} -f ${THISMAKEFILE} -j4 $t 2>&1 | grep -v "^--- "
18 # Within each test, the names of the sub-targets follow these
34 PARALLEL_TARG= ${.TARGET:C/\.[a-z]/.*/g:Q}
49 # shared: both shared.1.99 and shared.2.99 depend on shared.0.
50 # shared.0 must be made first, even though it is a child of
53 shared.1.99: shared.0 _ECHOUSE
54 shared.2.99: shared.2.1 shared.0 _ECHOUSE
56 # cycle: the cyclic dependency must not cause infinite recursion
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp1 //===- ScoreboardHazardRecognizer.cpp - Scheduler Support -----------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // encapsultes hazard-avoidance heuristics for scheduling, based on the
13 //===----------------------------------------------------------------------===//
18 #include "llvm/Config/llvm-config.h"
36 // the scoreboard. We always make the scoreboard at least 1 cycle deep to in ScoreboardHazardRecognizer()
39 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
40 for (unsigned idx = 0; ; ++idx) { in ScoreboardHazardRecognizer()
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H A DMachineCycleAnalysis.cpp1 //===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
22 char MachineCycleInfoWrapperPass::ID = 0;
29 INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles",
30 "Machine Cycle Info Analysis", true, true)
31 INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles",
32 "Machine Cycle Info Analysis", true, true)
48 OS << "MachineCycleInfo for function: " << F->getName() << "\n"; in print()
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dpwm-regulator.txt7 predefined voltage <=> duty-cycle values must be
10 Intermediary duty-cycle values which would normally
13 the user if the assumptions made in continuous-voltage
18 regulator-{min,max}-microvolt properties to calculate
19 appropriate duty-cycle values. This allows for a much
21 voltage-table mode above. This solution does make an
22 assumption that a %50 duty-cycle value will cause the
27 --------------------
28 - compatible: Should be "pwm-regulator"
30 - pwms: PWM specification (See: ../pwm/pwm.txt)
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H A Dpwm-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
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/freebsd/share/doc/psd/18.gprof/
H A Dpostp.me60 .ce 0
88 In these cases, we discover strongly-connected
92 We use a variation of Tarjan's strongly-connected
94 that discovers strongly-connected components as it is assigning
99 For example, a self-recursive routine
100 (a trivial cycle in the call graph)
109 Time is not propagated from one member of a cycle to another,
112 In addition, children of one member of a cycle
113 must be considered children of all members of the cycle.
114 Similarly, parents of one member of the cycle must inherit
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h1 //===- ModuloSchedule.h - Software pipeline schedule expansion ------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
18 // A schedule is, for every instruction in a block, a Cycle and a Stage. Note
19 // that we only support single-block loops, so "block" and "loop" can be used
22 // The Cycle of an instruction defines a partial order of the instructions in
23 // the remapped loop. Instructions within a cycle must not consume the output
24 // of any instruction in the same cycle. Cycle information is assumed to have
26 // lock-step (for example in a VLIW ISA).
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H A DMachinePipeliner.h1 //===- MachinePipeliner.h - Machine Software Pipeliner Pass -------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
18 // "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa,
22 // "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J.
28 // Urbana-Champaign, 2005.
39 //===----------------------------------------------------------------------===//
78 unsigned II_setByPragma = 0;
122 unsigned MII = 0;
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H A DScheduleHazardRecognizer.h1 //=- llvm/CodeGen/ScheduleHazardRecognizer.h - Scheduling Support -*- C++ -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // hazard-avoidance heuristics for scheduling.
12 //===----------------------------------------------------------------------===//
22 /// HazardRecognizer - This determines whether or not an instruction can be
23 /// issued this cycle, and whether or not a noop needs to be inserted to handle
27 /// MaxLookAhead - Indicate the number of cycles in the scoreboard
29 /// MaxLookAhead=0 identifies a fake recognizer, allowing the client to
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H A DScoreboardHazardRecognizer.h1 //=- llvm/CodeGen/ScoreboardHazardRecognizer.h - Schedule Support -*- C++ -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // encapsulates hazard-avoidance heuristics for scheduling, based on the
13 //===----------------------------------------------------------------------===//
30 // Scoreboard to track function unit usage. Scoreboard[0] is a
31 // mask of the FUs in use in the cycle currently being
32 // schedule. Scoreboard[1] is a mask for the next cycle. The
33 // Scoreboard is used as a circular buffer with the current cycle
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/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
7 "EventCode": "0xCA",
11 "UMask": "0x1e"
15 "Counter": "0,1,2,3",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
17 "EventCode": "0xCA",
21 "UMask": "0x10"
25 "Counter": "0,1,2,3",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
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/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
7 "EventCode": "0xCA",
11 "UMask": "0x1e"
15 "Counter": "0,1,2,3",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
17 "EventCode": "0xCA",
21 "UMask": "0x10"
25 "Counter": "0,1,2,3",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
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/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dpwm-vibrator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
23 const: pwm-vibrator
25 pwm-names:
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H A Dpwm-vibrator.txt4 strength increases based on the duty cycle of the enable PWM channel
5 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
8 driven at fixed duty cycle. If available this is can be used to increase
12 - compatible: should contain "pwm-vibrator"
13 - pwm-names: Should contain "enable" and optionally "direction"
14 - pwms: Should contain a PWM handle for each entry in pwm-names
17 - vcc-supply: Phandle for the regulator supplying power
18 - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
26 pinctrl-single,pins = <
27 OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
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/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A Dfloating-point.json4 "EventCode": "0x00",
6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
7 "UMask": "0x0f"
11 "EventCode": "0x00",
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
14 "UMask": "0x08"
18 "EventCode": "0x00",
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
21 "UMask": "0x04"
25 "EventCode": "0x00",
[all …]

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