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Searched +full:ctx +full:- +full:asid (Results 1 – 10 of 10) sorted by relevance

/freebsd/crypto/openssl/crypto/x509/
H A Dv3_asid.c2 * Copyright 2006-2024 The OpenSSL Project Authors. All Rights Reserved.
71 switch (choice->type) {
76 for (i = 0; i < sk_ASIdOrRange_num(choice->u.asIdsOrRanges); i++) {
78 sk_ASIdOrRange_value(choice->u.asIdsOrRanges, i);
79 switch (aor->type) {
81 if ((s = i2s_ASN1_INTEGER(NULL, aor->u.id)) == NULL)
87 if ((s = i2s_ASN1_INTEGER(NULL, aor->u.range->min)) == NULL)
89 BIO_printf(out, "%*s%s-", indent + 2, "", s);
91 if ((s = i2s_ASN1_INTEGER(NULL, aor->u.range->max)) == NULL)
113 ASIdentifiers *asid = ext; in i2r_ASIdentifiers() local
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/freebsd/sys/arm64/iommu/
H A Dsmmu.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2019-2020 Ruslan Bukin <br@bsdpad.com>
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
39 * In case of PCI-based devices, StreamID is a PCI rid.
42 * which contains per-device configuration.
44 * Stream table is a linear or 2-level walk table (this driver supports both).
50 * level 0 of page tables, ASID, etc.
67 * Register interface and Memory-based circular buffer queues are used
79 * in a producer-consumer fashion so that an output queue contains data
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/freebsd/sys/amd64/vmm/amd/
H A Dsvm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 #define AMD_CPUID_SVM_FLUSH_BY_ASID BIT(6) /* Flush by ASID */
110 static MALLOC_DEFINE(M_SVM_VLAPIC, "svm-vlapic", "svm-vlapic");
125 /* Current ASID generation for each host cpu */
126 static struct asid asid[MAXCPU]; variable
265 * The next ASID allocation will rollover both 'gen' and 'num' in svm_modinit()
268 asid[cpu].gen = ~0UL; in svm_modinit()
269 asid[cpu].num = nasid - 1; in svm_modinit()
301 ctrl->tsc_offset = offset; in svm_set_tsc_offset()
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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
16 to non-secure vs secure interrupt line.
21 - items:
22 - enum:
23 - qcom,msm8916-iommu
24 - qcom,msm8953-iommu
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/freebsd/crypto/openssl/include/openssl/
H A Dx509v3.h.in2 * {- join("\n * ", @autowarntext) -}
4 * Copyright 1999-2023 The OpenSSL Project Authors. All Rights Reserved.
12 {-
14 -}
48 struct v3_ext_ctx *ctx,
53 struct v3_ext_ctx *ctx, const char *str);
57 struct v3_ext_ctx *ctx, const char *str);
74 /* The following pair is used for multi-valued extensions */
110 {-
112 -}
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H A Dx509v3.h5 * Copyright 1999-2023 The OpenSSL Project Authors. All Rights Reserved.
47 struct v3_ext_ctx *ctx,
52 struct v3_ext_ctx *ctx, const char *str);
56 struct v3_ext_ctx *ctx, const char *str);
73 /* The following pair is used for multi-valued extensions */
300 # define CRL_REASON_NONE -1
605 "section:", (val)->section, \
606 ",name:", (val)->name, ",value:", (val)->value)
608 # define X509V3_set_ctx_test(ctx) \ argument
609 X509V3_set_ctx(ctx, NULL, NULL, NULL, NULL, X509V3_CTX_TEST)
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
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/freebsd/sys/riscv/vmm/
H A Driscv.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
81 uint64_t asid; member
114 struct hypctx *ctx[]; member
/freebsd/sys/arm64/arm64/
H A Dpmap.c1 /*-
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
52 /*-
59 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
90 * this module may throw away valid virtual-to-physical
92 * of virtual-to-physical mappings must be done as
96 * make virtual-to-physical map invalidates expensive,
160 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
161 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
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H A Didentcpu.c1 /*-
91 * The default implementation of I-cache sync assumes we have an
106 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) in sysctl_hw_machine()
125 * Per-CPU affinity as provided in MPIDR_EL1
131 * Aff1 - Cluster number
132 * Aff0 - CPU number in Aff1 cluster
180 return (&cpu_desc[cpu - 1]); in get_cpu_desc()
201 * Per-implementer table of (PartNum, CPU Name) pairs.
206 { CPU_PART_FOUNDATION, "Foundation-Model" },
207 { CPU_PART_CORTEX_A34, "Cortex-A34" },
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