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Searched full:ctrl_reg (Results 1 – 25 of 51) sorted by relevance

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/linux/drivers/clk/microchip/
H A Dclk-pic32.c90 void __iomem *ctrl_reg; member
100 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
107 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
115 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
146 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; in pbclk_read_pbdiv()
175 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
186 v = readl(pb->ctrl_reg); in pbclk_set_rate()
192 writel(v, pb->ctrl_reg); in pbclk_set_rate()
197 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
227 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; in pic32_periph_clk_register()
[all …]
H A Dclk-pic32.h21 const u32 ctrl_reg; member
38 const u32 ctrl_reg; member
45 const u32 ctrl_reg; member
H A Dclk-pic32mzda.c29 .ctrl_reg = (__reg), \
43 .ctrl_reg = (__reg), \
97 .ctrl_reg = 0x020,
/linux/drivers/pci/hotplug/
H A Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST), argument
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved1),
[all …]
/linux/drivers/ntb/hw/epf/
H A Dntb_hw_epf.c112 void __iomem *ctrl_reg; member
135 writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT); in ntb_epf_send_command()
136 writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND); in ntb_epf_send_command()
141 status = readw(ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
159 writew(0, ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
227 status = readw(ndev->ctrl_reg + NTB_EPF_LINK_STATUS); in ntb_epf_link_is_up()
243 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_read()
246 return readl(ndev->ctrl_reg + offset); in ntb_epf_spad_read()
261 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_write()
263 writel(val, ndev->ctrl_reg + offset); in ntb_epf_spad_write()
[all …]
/linux/drivers/thermal/
H A Dloongson2_thermal.c44 void __iomem *ctrl_reg; member
54 int ctrl_reg = low ? LOONGSON2_THSENS_CTRL_LOW_REG : LOONGSON2_THSENS_CTRL_HI_REG; in loongson2_set_ctrl_regs() local
58 writew(reg_ctrl, data->ctrl_reg + ctrl_reg + reg_off); in loongson2_set_ctrl_regs()
78 val = readl(data->ctrl_reg + LOONGSON2_THSENS_OUT_REG); in loongson2_2k1000_get_temp()
100 writeb(LOONGSON2_THSENS_INT_EN, data->ctrl_reg + LOONGSON2_THSENS_STATUS_REG); in loongson2_thermal_irq_thread()
138 data->ctrl_reg = devm_platform_ioremap_resource(pdev, 0); in loongson2_thermal_probe()
139 if (IS_ERR(data->ctrl_reg)) in loongson2_thermal_probe()
140 return PTR_ERR(data->ctrl_reg); in loongson2_thermal_probe()
157 writeb(LOONGSON2_THSENS_INT_EN, data->ctrl_reg + LOONGSON2_THSENS_STATUS_REG); in loongson2_thermal_probe()
/linux/drivers/net/wireless/silabs/wfx/
H A Dbh.c137 int ctrl_reg, piggyback; in bh_work_rx() local
142 ctrl_reg = piggyback; in bh_work_rx()
144 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0); in bh_work_rx()
146 ctrl_reg = 0; in bh_work_rx()
147 if (!(ctrl_reg & CTRL_NEXT_LEN_MASK)) in bh_work_rx()
149 /* ctrl_reg units are 16bits words */ in bh_work_rx()
150 len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2; in bh_work_rx()
159 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggyback); in bh_work_rx()
161 if (ctrl_reg) in bh_work_rx()
163 ctrl_reg, piggyback); in bh_work_rx()
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/linux/drivers/phy/marvell/
H A Dphy-berlin-sata.c66 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, in phy_berlin_sata_reg_setbits() argument
72 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); in phy_berlin_sata_reg_setbits()
75 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
78 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
85 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on() local
105 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, in phy_berlin_sata_power_on()
110 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, in phy_berlin_sata_power_on()
114 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, in phy_berlin_sata_power_on()
118 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, in phy_berlin_sata_power_on()
122 regval = readl(ctrl_reg + PORT_SCR_CTL); in phy_berlin_sata_power_on()
[all …]
/linux/drivers/misc/ibmasm/
H A Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
54 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
60 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/linux/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c136 u32 ctrl_reg; member
148 void __iomem *ctrl_reg; member
174 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
176 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
178 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
203 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
205 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
218 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
221 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
236 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
[all …]
/linux/drivers/input/rmi4/
H A Drmi_f30.c275 u8 *ctrl_reg = f30->ctrl_regs; in rmi_f30_initialize() local
300 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
303 sizeof(u8), &ctrl_reg); in rmi_f30_initialize()
307 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
310 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
315 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
319 &ctrl_reg); in rmi_f30_initialize()
325 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
331 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
336 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
[all …]
/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c113 u32 ctrl_reg; in ttc_set_interval() local
116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
117 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
126 ctrl_reg |= CNT_CNTRL_RESET; in ttc_set_interval()
127 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
201 u32 ctrl_reg; in ttc_shutdown() local
203 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
204 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_shutdown()
[all …]
H A Dtimer-rockchip.c133 u32 ctrl_reg = TIMER_CONTROL_REG3288; in rk_timer_probe() local
142 ctrl_reg = TIMER_CONTROL_REG3399; in rk_timer_probe()
144 timer->ctrl = timer->base + ctrl_reg; in rk_timer_probe()
/linux/drivers/spi/
H A Dspi-cadence.c167 u32 ctrl_reg = 0; in cdns_spi_init_hw() local
170 ctrl_reg |= CDNS_SPI_CR_DEFAULT; in cdns_spi_init_hw()
173 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; in cdns_spi_init_hw()
183 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_init_hw()
195 u32 ctrl_reg; in cdns_spi_chipselect() local
197 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); in cdns_spi_chipselect()
201 ctrl_reg |= CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
204 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
206 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) << in cdns_spi_chipselect()
210 ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) & in cdns_spi_chipselect()
[all …]
/linux/drivers/fpga/
H A Dsocfpga.c338 u32 ctrl_reg; in socfpga_fpga_cfg_mode_set() local
347 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_cfg_mode_set()
348 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK; in socfpga_fpga_cfg_mode_set()
349 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK; in socfpga_fpga_cfg_mode_set()
350 ctrl_reg |= cfgmgr_modes[mode].ctrl; in socfpga_fpga_cfg_mode_set()
353 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE; in socfpga_fpga_cfg_mode_set()
354 socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); in socfpga_fpga_cfg_mode_set()
362 u32 ctrl_reg, status; in socfpga_fpga_reset() local
379 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_reset()
380 ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL; in socfpga_fpga_reset()
[all …]
/linux/drivers/regulator/
H A Dvctrl-regulator.c323 struct regulator *ctrl_reg) in vctrl_init_vtable() argument
332 n_voltages = regulator_count_voltages(ctrl_reg); in vctrl_init_vtable()
338 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
358 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
450 struct regulator *ctrl_reg; in vctrl_probe() local
465 ctrl_reg = devm_regulator_get(&pdev->dev, "ctrl"); in vctrl_probe()
466 if (IS_ERR(ctrl_reg)) in vctrl_probe()
467 return PTR_ERR(ctrl_reg); in vctrl_probe()
477 if ((regulator_get_linear_step(ctrl_reg) == 1) || in vctrl_probe()
478 (regulator_count_voltages(ctrl_reg) == -EINVAL)) { in vctrl_probe()
[all …]
/linux/drivers/watchdog/
H A Dmeson_gxbb_wdt.c166 u32 ctrl_reg; in meson_gxbb_wdt_probe() local
194 ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) & in meson_gxbb_wdt_probe()
197 if (ctrl_reg) { in meson_gxbb_wdt_probe()
207 ctrl_reg |= ((clk_get_rate(data->clk) / 1000) & in meson_gxbb_wdt_probe()
213 writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG); in meson_gxbb_wdt_probe()
/linux/drivers/net/wireless/realtek/rtw88/
H A Dsec.c127 u16 ctrl_reg; in rtw_sec_enable_sec_engine() local
133 ctrl_reg = rtw_read16(rtwdev, REG_CR); in rtw_sec_enable_sec_engine()
134 ctrl_reg |= RTW_SEC_ENGINE_EN; in rtw_sec_enable_sec_engine()
135 rtw_write16(rtwdev, REG_CR, ctrl_reg); in rtw_sec_enable_sec_engine()
/linux/drivers/rtc/
H A Drtc-rk808.c45 unsigned int ctrl_reg; member
103 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_readtime()
117 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_readtime()
163 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_set_time()
178 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_set_time()
363 .ctrl_reg = RK808_RTC_CTRL_REG,
371 .ctrl_reg = RK817_RTC_CTRL_REG,
403 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_probe()
H A Drtc-spear.c27 #define CTRL_REG 0x10 macro
101 val = readl(config->ioaddr + CTRL_REG); in spear_rtc_enable_interrupt()
105 writel(val, config->ioaddr + CTRL_REG); in spear_rtc_enable_interrupt()
113 val = readl(config->ioaddr + CTRL_REG); in spear_rtc_disable_interrupt()
116 writel(val, config->ioaddr + CTRL_REG); in spear_rtc_disable_interrupt()
273 alm->enabled = readl(config->ioaddr + CTRL_REG) & INT_ENABLE; in spear_rtc_read_alarm()
/linux/drivers/media/platform/ti/davinci/
H A Dvpif.h391 u32 ctrl_reg; in disable_raw_feature() local
393 ctrl_reg = VPIF_CH0_CTRL; in disable_raw_feature()
395 ctrl_reg = VPIF_CH1_CTRL; in disable_raw_feature()
398 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in disable_raw_feature()
400 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in disable_raw_feature()
405 u32 ctrl_reg; in enable_raw_feature() local
407 ctrl_reg = VPIF_CH0_CTRL; in enable_raw_feature()
409 ctrl_reg = VPIF_CH1_CTRL; in enable_raw_feature()
412 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in enable_raw_feature()
414 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in enable_raw_feature()
/linux/arch/arm64/kernel/
H A Dhw_breakpoint.c230 int i, max_slots, ctrl_reg, val_reg, reg_enable; in hw_breakpoint_control() local
236 ctrl_reg = AARCH64_DBG_REG_BCR; in hw_breakpoint_control()
243 ctrl_reg = AARCH64_DBG_REG_WCR; in hw_breakpoint_control()
269 write_wb_reg(ctrl_reg, i, in hw_breakpoint_control()
274 write_wb_reg(ctrl_reg, i, 0); in hw_breakpoint_control()
634 u32 ctrl_reg; in do_breakpoint() local
658 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i); in do_breakpoint()
659 decode_ctrl_reg(ctrl_reg, &ctrl); in do_breakpoint()
766 u32 ctrl_reg; in do_watchpoint() local
796 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i); in do_watchpoint()
[all …]
/linux/arch/arm/kernel/
H A Dhw_breakpoint.c298 u32 ctrl_reg; in get_max_wp_len() local
307 ctrl_reg = encode_ctrl_reg(ctrl); in get_max_wp_len()
310 write_wb_reg(ARM_BASE_WCR, ctrl_reg); in get_max_wp_len()
311 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) in get_max_wp_len()
732 u32 val, ctrl_reg; in watchpoint_handler() local
769 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); in watchpoint_handler()
770 decode_ctrl_reg(ctrl_reg, &ctrl); in watchpoint_handler()
857 u32 ctrl_reg, val, addr; in breakpoint_handler() local
884 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); in breakpoint_handler()
885 decode_ctrl_reg(ctrl_reg, &ctrl); in breakpoint_handler()
/linux/drivers/comedi/drivers/
H A Ddas16.c434 unsigned int ctrl_reg; member
479 if (!(devpriv->ctrl_reg & DAS16_CTRL_DMAE)) { in das16_interrupt()
746 devpriv->ctrl_reg &= ~(DAS16_CTRL_INTE | DAS16_CTRL_PACING_MASK); in das16_cmd_exec()
747 devpriv->ctrl_reg |= DAS16_CTRL_DMAE; in das16_cmd_exec()
749 devpriv->ctrl_reg |= DAS16_CTRL_EXT_PACER; in das16_cmd_exec()
751 devpriv->ctrl_reg |= DAS16_CTRL_INT_PACER; in das16_cmd_exec()
752 outb(devpriv->ctrl_reg, dev->iobase + DAS16_CTRL_REG); in das16_cmd_exec()
770 devpriv->ctrl_reg &= ~(DAS16_CTRL_INTE | DAS16_CTRL_DMAE | in das16_cancel()
772 outb(devpriv->ctrl_reg, dev->iobase + DAS16_CTRL_REG); in das16_cancel()
1177 devpriv->ctrl_reg = DAS16_CTRL_IRQ(dev->irq); in das16_attach()
[all …]
/linux/drivers/mailbox/
H A Dsun6i-msgbox.c22 #define CTRL_REG(n) (0x0000 + 0x4 * ((n) / 4)) macro
106 if (WARN_ON_ONCE(!(readl(mbox->regs + CTRL_REG(n)) & CTRL_TX(n)))) in sun6i_msgbox_send_data()
121 if (readl(mbox->regs + CTRL_REG(n)) & CTRL_RX(n)) { in sun6i_msgbox_startup()
144 if (readl(mbox->regs + CTRL_REG(n)) & CTRL_RX(n)) { in sun6i_msgbox_shutdown()

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