xref: /linux/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml (revision 16e6a1a3cb3fa5fa11cd76a9d71235d927923329) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC MIPI RX0 D-PHY
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |
13  The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
14  connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
15
16properties:
17  compatible:
18    enum:
19      - rockchip,px30-csi-dphy
20      - rockchip,rk1808-csi-dphy
21      - rockchip,rk3326-csi-dphy
22      - rockchip,rk3368-csi-dphy
23      - rockchip,rk3568-csi-dphy
24      - rockchip,rk3588-csi-dphy
25
26  reg:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  clock-names:
33    const: pclk
34
35  '#phy-cells':
36    const: 0
37
38  power-domains:
39    description: Video in/out power domain.
40    maxItems: 1
41
42  resets:
43    items:
44      - description: APB reset line
45      - description: PHY reset line
46    minItems: 1
47
48  reset-names:
49    items:
50      - const: apb
51      - const: phy
52    minItems: 1
53
54  rockchip,grf:
55    $ref: /schemas/types.yaml#/definitions/phandle
56    description:
57      Some additional phy settings are access through GRF regs.
58
59  rockchip,clk-lane-phase:
60    $ref: /schemas/types.yaml#/definitions/uint32
61    minimum: 0
62    maximum: 7
63    default: 3
64    description:
65      Clock lane sampling phase selection (hardware tap index 0–7). Each step
66      corresponds to an approximately 40 ps delay as described in the hardware
67      specification.
68
69required:
70  - compatible
71  - reg
72  - clocks
73  - clock-names
74  - '#phy-cells'
75  - resets
76  - reset-names
77  - rockchip,grf
78
79allOf:
80  - if:
81      properties:
82        compatible:
83          contains:
84            enum:
85              - rockchip,px30-csi-dphy
86              - rockchip,rk1808-csi-dphy
87              - rockchip,rk3326-csi-dphy
88              - rockchip,rk3368-csi-dphy
89    then:
90      required:
91        - power-domains
92  - if:
93      properties:
94        compatible:
95          contains:
96            enum:
97              - rockchip,px30-csi-dphy
98              - rockchip,rk1808-csi-dphy
99              - rockchip,rk3326-csi-dphy
100              - rockchip,rk3368-csi-dphy
101              - rockchip,rk3568-csi-dphy
102    then:
103      properties:
104        resets:
105          maxItems: 1
106
107        reset-names:
108          maxItems: 1
109    else:
110      properties:
111        resets:
112          minItems: 2
113
114        reset-names:
115          minItems: 2
116
117additionalProperties: false
118
119examples:
120  - |
121
122    csi_dphy: phy@ff2f0000 {
123        compatible = "rockchip,px30-csi-dphy";
124        reg = <0xff2f0000 0x4000>;
125        clocks = <&cru 1>;
126        clock-names = "pclk";
127        #phy-cells = <0>;
128        power-domains = <&power 1>;
129        resets = <&cru 1>;
130        reset-names = "apb";
131        rockchip,grf = <&grf>;
132    };
133  - |
134    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
135    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
136
137    soc {
138        #address-cells = <2>;
139        #size-cells = <2>;
140
141        phy@fedc0000 {
142            compatible = "rockchip,rk3588-csi-dphy";
143            reg = <0x0 0xfedc0000 0x0 0x8000>;
144            clocks = <&cru PCLK_CSIPHY0>;
145            clock-names = "pclk";
146            #phy-cells = <0>;
147            resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
148            reset-names = "apb", "phy";
149            rockchip,grf = <&csidphy0_grf>;
150        };
151    };
152