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/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
36 - const: csi-bridge
39 - const: mipi-csi
47 - const: csi-bridge-axi
48 - const: csi-bridge-apb
49 - const: csi-bridge-core
55 - const: csi-aclk
56 - const: csi-pclk
78 power-domain-names = "bus", "csi-bridge", "lcdif",
79 "mipi-dsi", "mipi-csi";
[all …]
H A Dfsl,imx8mn-disp-blk-ctrl.yaml14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
39 - const: mipi-csi
56 - const: csi-aclk
57 - const: csi-pclk
81 "mipi-csi";
95 "dsi-ref", "csi-aclk", "csi-pclk";
/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml7 title: Xilinx MIPI CSI-2 Receiver Subsystem
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
47 xlnx,csi-pxl-format:
49 This denotes the CSI Data type selected in hw design.
79 xlnx,en-csi-v2-0:
81 description: Present if CSI v2 is enabled in IP configuration.
107 CSI-2 transmitter.
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dnxp,imx7-csi.yaml4 $id: http://devicetree.org/schemas/media/nxp,imx7-csi.yaml#
7 title: i.MX7 and i.MX8 CSI bridge (CMOS Sensor Interface)
13 This is device node for the CMOS Sensor Interface (CSI) which enables the
20 - fsl,imx8mq-csi
21 - fsl,imx7-csi
22 - fsl,imx6ul-csi
24 - const: fsl,imx8mm-csi
25 - const: fsl,imx7-csi
62 - fsl,imx8mm-csi
73 csi
[all...]
H A Dimx7-csi.txt4 csi node
7 This is device node for the CMOS Sensor Interface (CSI) which enables the chip
12 - compatible : "fsl,imx7-csi" or "fsl,imx6ul-csi";
14 - interrupts : should contain CSI interrupt;
27 csi: csi@30710000 {
31 compatible = "fsl,imx7-csi";
H A Dallwinner,sun6i-a31-csi.yaml4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
7 title: Allwinner A31 CMOS Sensor Interface (CSI)
16 - allwinner,sun6i-a31-csi
17 - allwinner,sun8i-a83t-csi
18 - allwinner,sun8i-h3-csi
19 - allwinner,sun8i-v3s-csi
20 - allwinner,sun50i-a64-csi
74 description: MIPI CSI-2 bridge input port
108 csi1: csi@1cb4000 {
109 compatible = "allwinner,sun8i-v3s-csi";
H A Dallwinner,sun4i-a10-csi.yaml4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
7 title: Allwinner A10 CMOS Sensor Interface (CSI)
38 - description: The CSI interface clock
39 - description: The CSI DRAM clock
42 - description: The CSI interface clock
43 - description: The CSI ISP clock
44 - description: The CSI DRAM clock
109 csi0: csi@1c09000 {
H A Drenesas,rzg2l-csi2.yaml8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
66 Input port node, single endpoint describing the CSI-2 transmitter.
87 Output port node, Image Processing block connected to the CSI-2 receiver.
111 csi: csi@10830400 {
H A Dti,omap3isp.txt14 CSI PHYs and receivers registers.
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
42 vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
43 vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
48 lane-polarities : lane polarity (required on CSI-2)
51 be either 1 or 2. (required on CSI-2)
52 clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
22 csi@3,0 {
23 compatible = "ifm,o2d-csi";
27 ifm,csi-clk-handle = <&timer7>;
32 ifm,csi-addr-bus-width = <24>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Drockchip-inno-csi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
21 - rockchip,rk3326-csi-dphy
22 - rockchip,rk3368-csi-dphy
23 - rockchip,rk3568-csi-dphy
71 compatible = "rockchip,px30-csi-dphy";
H A Dmediatek,mt8365-csi-rx.yaml5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
23 - mediatek,mt8365-csi-rx
65 compatible = "mediatek,mt8365-csi-rx";
72 compatible = "mediatek,mt8365-csi-rx";
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_sifive_vector.td66 defm sf_vc_xv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe", [0, 2, 3], UseGPR=1>;
67 defm sf_vc_iv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz", [0, 2, 3], UseGPR=0>;
68 defm sf_vc_vv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv", [0, 2, 3], UseGPR=0>;
70 defm sf_vc_xvv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUe", [0, 1, 2, 3], UseGPR=1>;
71 defm sf_vc_ivv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvKz", [0, 1, 2, 3], UseGPR=0>;
72 defm sf_vc_vvv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUv", [0, 1, 2, 3], UseGPR=0>;
74 defm sf_vc_v_x : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzUe", [-1, 1, 2], UseGPR=1>;
75 defm sf_vc_v_i : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzKz", [-1, 1, 2], UseGPR=0>;
76 defm sf_vc_v_xv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUe", [-1, 0, 1, 2], UseGPR=1>;
77 defm sf_vc_v_iv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvKz", [-1, 0, 1, 2], UseGPR=0>;
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/freebsd/lib/libkiconv/
H A Dkiconv_sysctl.c69 struct iconv_cspair_info *csi, *csip; in kiconv_lookupcs() local
74 csi = malloc(size); in kiconv_lookupcs()
75 if (csi == NULL) in kiconv_lookupcs()
77 if (sysctlbyname("kern.iconv.cslist", csi, &size, NULL, 0) == -1) { in kiconv_lookupcs()
78 free(csi); in kiconv_lookupcs()
81 for (i = 0, csip = csi; i < (size/sizeof(*csi)); i++, csip++){ in kiconv_lookupcs()
84 free(csi); in kiconv_lookupcs()
88 free(csi); in kiconv_lookupcs()
/freebsd/sys/arm/allwinner/h6/
H A Dh6_padconf.c55 { "PD0", 3, 0, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
56 { "PD1", 3, 1, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
57 { "PD2", 3, 2, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
58 { "PD3", 3, 3, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
59 { "PD4", 3, 4, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
60 { "PD5", 3, 5, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
61 { "PD6", 3, 6, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
62 { "PD7", 3, 7, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
63 { "PD8", 3, 8, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
64 { "PD9", 3, 9, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
32 0 CSI-2 first input port
33 1 CSI-2 second input port
36 Endpoint node required property for CSI-2 connection is:
39 Endpoint node optional property for CSI-2 connection is:
H A Dtoshiba,tc358746.yaml13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
59 description: MIPI CSI phy voltage supply, 1.2 volts
137 csi-bridge@e {
/freebsd/sys/arm/allwinner/a83t/
H A Da83t_padconf.c93 { "PE0", 4, 0, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
94 { "PE1", 4, 1, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
95 { "PE2", 4, 2, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
96 { "PE3", 4, 3, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
97 { "PE4", 4, 4, { "gpio_in", "gpio_out", "csi" } },
98 { "PE5", 4, 5, { "gpio_in", "gpio_out", "csi" } },
99 { "PE6", 4, 6, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
100 { "PE7", 4, 7, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
101 { "PE8", 4, 8, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
102 { "PE9", 4, 9, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp66 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); in emitPrologue() local
68 if (!CSI.empty()) { in emitPrologue()
74 for (unsigned i = 0, e = CSI.size(); i < e; ++i) { in emitPrologue()
76 const CalleeSavedInfo &Info = CSI[i]; in emitPrologue()
98 for (const auto &I : CSI) { in emitPrologue()
154 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); in emitEpilogue() local
158 for (unsigned i = 0, e = CSI.size(); i < e; ++i) { in emitEpilogue()
161 const CalleeSavedInfo &Info = CSI[i]; in emitEpilogue()
195 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { in spillCalleeSavedRegisters() argument
199 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { in spillCalleeSavedRegisters()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.h54 ArrayRef<CalleeSavedInfo> CSI, in spillCalleeSavedRegisters() argument
62 MutableArrayRef<CalleeSavedInfo> CSI, in restoreCalleeSavedRegisters() argument
73 // Override this function to avoid calling hasFP before CSI is set in canSimplifyCallFramePseudos()
109 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
126 bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
128 bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
176 void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
178 bool shouldInlineCSR(const MachineFunction &MF, const CSIVect &CSI) const;
179 bool useSpillFunction(const MachineFunction &MF, const CSIVect &CSI) const;
180 bool useRestoreFunction(const MachineFunction &MF, const CSIVect &CSI) const;
/freebsd/sys/arm/allwinner/a64/
H A Da64_padconf.c93 { "PE0", 4, 0, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
94 { "PE1", 4, 1, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
95 { "PE2", 4, 2, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
96 { "PE3", 4, 3, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
97 { "PE4", 4, 4, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
98 { "PE5", 4, 5, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
99 { "PE6", 4, 6, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
100 { "PE7", 4, 7, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
101 { "PE8", 4, 8, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
102 { "PE9", 4, 9, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra210-csi.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
7 title: NVIDIA Tegra CSI controller
15 pattern: "^csi@[0-9a-f]+$"
19 - nvidia,tegra210-csi
34 - const: csi
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Do2d.dtsi97 csi@3,0 {
98 compatible = "ifm,o2d-csi";
100 ifm,csi-clk-handle = <&gpt7>;
107 ifm,csi-addr-bus-width = <24>;
108 ifm,csi-data-bus-width = <8>;
109 ifm,csi-wait-cycles = <0>;
/freebsd/sys/arm/allwinner/a33/
H A Da33_padconf.c87 {"PE0", 4, 0, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
88 {"PE1", 4, 1, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
89 {"PE2", 4, 2, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
90 {"PE3", 4, 3, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
91 {"PE4", 4, 4, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
92 {"PE5", 4, 5, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
93 {"PE6", 4, 6, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
94 {"PE7", 4, 7, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
95 {"PE8", 4, 8, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
96 {"PE9", 4, 9, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
[all …]
/freebsd/sys/arm/allwinner/h3/
H A Dh3_padconf.c101 {"PE0", 4, 0, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
102 {"PE1", 4, 1, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
103 {"PE2", 4, 2, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
104 {"PE3", 4, 3, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
105 {"PE4", 4, 4, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
106 {"PE5", 4, 5, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
107 {"PE6", 4, 6, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
108 {"PE7", 4, 7, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
109 {"PE8", 4, 8, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
110 {"PE9", 4, 9, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
[all …]

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