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/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
[all …]
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
9 GPIOs (strictly in this order).
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
15 peripherals located in the DISP domain of the SoC.
20 - const: fsl,imx8mm-disp-blk-ctrl
[all …]
H A Dfsl,imx8mn-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MN DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
15 peripherals located in the DISP domain of the SoC.
20 - const: fsl,imx8mn-disp-blk-ctrl
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_sifive_vector.td1 //==--- riscv_sifive_vector.td - RISC-V SiFive VCIX function list ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the builtins for RISC-V SiFive VCIX. See:
11 // https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software…
13 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
51 foreach r = range in
53 ["Xsfvcp", "RV64"], ["Xsfvcp"]) in
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dimx7-csi.txt4 csi node
5 --------
7 This is device node for the CMOS Sensor Interface (CSI) which enables the chip
12 - compatible : "fsl,imx7-csi" or "fsl,imx6ul-csi";
13 - reg : base address and length of the register set for the device;
14 - interrupts : should contain CSI interrupt;
15 - clocks : list of clock specifiers, see
16 Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17 - clock-names : must contain "mclk";
20 node, according to the bindings defined in:
[all …]
H A Dti,omap3isp.txt4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
14 CSI PHYs and receivers registers.
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
29 More documentation on these bindings is available in
[all …]
H A Drenesas,rzg2l-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
21 - enum:
22 - renesas,r9a07g043-csi2 # RZ/G2UL
[all …]
H A Dimx.txt5 ---------------------------
12 - compatible : "fsl,imx-capture-subsystem";
13 - ports : Should contain a list of phandles pointing to camera
18 capture-subsystem {
19 compatible = "fsl,imx-capture-subsystem";
25 --------------
27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29 combined with a D-PHY core mixed into the same register block. In
30 addition this device consists of an i.MX-specific "CSI2IPU gasket"
[all …]
H A Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interface
[all...]
/freebsd/lib/libkiconv/
H A Dkiconv_sysctl.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
7 * Redistribution and use in source and binary forms, with or without
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43 if (sysctlbyname("kern.iconv.drvlist", NULL, &size, NULL, 0) == -1) in kiconv_lookupconv()
51 if (sysctlbyname("kern.iconv.drvlist", drivers, &size, NULL, 0) == -1) { in kiconv_lookupconv()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Drockchip-inno-csi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-inn
[all...]
H A Dmediatek,mt8365-csi-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
11 - Julien Stephan <jstephan@baylibre.com>
12 - Andy Hsieh <andy.hsieh@mediatek.com>
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
17 Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
23 - mediatek,mt8365-csi-rx
[all …]
/freebsd/sys/arm/allwinner/h6/
H A Dh6_padconf.c1 /*-
4 * Redistribution and use in source and binary forms, with or without
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55 { "PD0", 3, 0, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
56 { "PD1", 3, 1, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
57 { "PD2", 3, 2, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
18 - VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
[all …]
H A Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/arm/allwinner/a83t/
H A Da83t_padconf.c1 /*-
4 * Redistribution and use in source and binary forms, with or without
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
93 { "PE0", 4, 0, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
94 { "PE1", 4, 1, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
95 { "PE2", 4, 2, { "gpio_in", "gpio_out", "csi", NULL, "ccir" } },
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.h1 //==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
43 // callee-saved registers is handled in emitPrologue. This is to have the
44 // logic for shrink-wrapping in one place.
54 ArrayRef<CalleeSavedInfo> CSI, in spillCalleeSavedRegisters() argument
62 MutableArrayRef<CalleeSavedInfo> CSI, in restoreCalleeSavedRegisters() argument
73 // Override this function to avoid calling hasFP before CSI is set in canSimplifyCallFramePseudos()
97 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
98 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 }, in getCalleeSavedSpillSlots()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp1 //===- XtensaFrameLowering.cpp - Xtensa Frame Information -----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
38 assert(&MBB == &MF.front() && "Shrink-wrapping not yet implemented"); in emitPrologue()
41 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); in emitPrologue()
43 MCRegister FP = TRI->getFrameRegister(MF); in emitPrologue()
51 StackSize += (16 - StackSize) & 0xf; in emitPrologue()
58 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); in emitPrologue()
66 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); in emitPrologue() local
[all …]
/freebsd/sys/arm/allwinner/a64/
H A Da64_padconf.c1 /*-
4 * Redistribution and use in source and binary forms, with or without
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
93 { "PE0", 4, 0, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
94 { "PE1", 4, 1, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
95 { "PE2", 4, 2, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFrameLowering.cpp1 //===-- LoongArchFrameLowering.cpp - LoongArch Frame Information -*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "loongarch-frame-lowering"
39 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
47 return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(MF); in hasBP()
64 BuildMI(MBB, MBBI, DL, TII->get(Addi), DestReg) in adjustReg()
73 // in each ADDI. In the negative direction, we can use -2048 which is always in adjustReg()
74 // sufficiently aligned. In the positive direction, we need to find the in adjustReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerSGPRSpills.cpp1 //===-- SILowerSGPRSPills.cpp ---------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 // FIXME: Must stop RegScavenger spills in later passes.
16 //===----------------------------------------------------------------------===//
29 #define DEBUG_TYPE "si-lower-sgpr-spills"
85 /// Insert spill code for the callee-saved registers used in the function.
87 ArrayRef<CalleeSavedInfo> CSI, SlotIndexes *Indexes, in insertCSRSaves() argument
97 if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) { in insertCSRSaves()
100 for (const CalleeSavedInfo &CS : CSI) { in insertCSRSaves()
[all …]
/freebsd/sys/arm/allwinner/h3/
H A Dh3_padconf.c1 /*-
2 * Copyright (c) 2016-2017 Emmanuel Vadot <manu@freebsd.org>
4 * Redistribution and use in source and binary forms, with or without
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
101 {"PE0", 4, 0, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
102 {"PE1", 4, 1, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}},
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp1 //===-- RISCVFrameLowering.cpp - RISC-V Frame Information -----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the RISC-V implementation of TargetFrameLowering class.
11 //===----------------------------------------------------------------------===//
48 {/*ra*/ RISCV::X1, -1}, {/*s0*/ RISCV::X8, -2},
49 {/*s1*/ RISCV::X9, -3}, {/*s2*/ RISCV::X18, -4},
50 {/*s3*/ RISCV::X19, -5}, {/*s4*/ RISCV::X20, -6},
51 {/*s5*/ RISCV::X21, -7}, {/*s6*/ RISCV::X22, -8},
52 {/*s7*/ RISCV::X23, -9}, {/*s8*/ RISCV::X24, -10},
[all …]
/freebsd/sys/arm/allwinner/a33/
H A Da33_padconf.c1 /*-
4 * Redistribution and use in source and binary forms, with or without
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
87 {"PE0", 4, 0, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
88 {"PE1", 4, 1, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
89 {"PE2", 4, 2, {"gpio_in", "gpio_out", "csi", NULL, NULL, NULL, NULL, NULL}, 0, 0},
[all …]

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