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/linux/Documentation/devicetree/bindings/gpio/
H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST Microelectronics SPEAr SPI CS GPIO Controller
10 - Viresh Kumar <vireshk@kernel.org>
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
37 st-spics,peripcfg-reg:
[all …]
/linux/drivers/clocksource/
H A Dem_sti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
61 iowrite32(value, p->base + offs); in em_sti_write()
68 /* enable clock */ in em_sti_enable()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
79 /* mask and clear pending interrupts */ in em_sti_enable()
83 /* enable updates of counter registers */ in em_sti_enable()
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H A Dtimer-pistachio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pistachio clocksource based on general-purpose timers
48 struct clocksource cs; member
53 #define to_pistachio_clocksource(cs) \ argument
54 container_of(cs, struct pistachio_clocksource, cs)
68 pistachio_clocksource_read_cycles(struct clocksource *cs) in pistachio_clocksource_read_cycles() argument
70 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles()
80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
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H A Dingenic-timer.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/mfd/ingenic-tcu.h>
23 #include <dt-bindings/clock/ingenic,tcu.h>
44 struct clocksource cs; member
56 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count); in ingenic_tcu_timer_read()
61 static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs) in ingenic_tcu_timer_cs_read() argument
69 return container_of(timer, struct ingenic_tcu, timers[timer->cpu]); in to_ingenic_tcu()
83 regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel)); in ingenic_tcu_cevt_set_state_shutdown()
95 return -EINVAL; in ingenic_tcu_cevt_set_next()
97 regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next); in ingenic_tcu_cevt_set_next()
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H A Dsh_cmt.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
106 struct clocksource cs; member
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H A Dingenic-ost.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/mfd/ingenic-tcu.h>
25 * The TCU_REG_OST_CNT{L,R} from <linux/mfd/ingenic-tcu.h> are only for the
39 struct clocksource cs; member
47 return readl(ingenic_ost->regs + OST_REG_CNTL); in ingenic_ost_read_cntl()
53 return readl(ingenic_ost->regs + OST_REG_CNTH); in ingenic_ost_read_cnth()
56 static u64 notrace ingenic_ost_clocksource_readl(struct clocksource *cs) in ingenic_ost_clocksource_readl() argument
61 static u64 notrace ingenic_ost_clocksource_readh(struct clocksource *cs) in ingenic_ost_clocksource_readh() argument
69 struct device *dev = &pdev->dev; in ingenic_ost_probe()
71 struct clocksource *cs; in ingenic_ost_probe() local
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/linux/include/linux/
H A Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
41 * @mask: Bitmask for two's complement
49 * @archdata: Optional arch-specific data
60 * 1-99: Unfit for real use
62 * 100-199: Base level usability.
64 * 200-299: Good.
66 * 300-399: Desired.
68 * 400-499: Perfect
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/linux/drivers/memory/
H A Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
83 struct device_node *np, u32 cs) in pl172_setup_static() argument
90 if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) { in pl172_setup_static()
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H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
207 /* Structure to save gpmc cs context */
258 /* Define chip-selects as reserved by default until probe completes */
278 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
282 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
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/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
23 static void clocksource_enqueue(struct clocksource *cs);
25 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
27 u64 delta = clocksource_delta(end, start, cs->mask, cs in cycles_to_nsec_safe()
195 clocksource_change_rating(struct clocksource * cs,int rating) clocksource_change_rating() argument
202 __clocksource_unstable(struct clocksource * cs) __clocksource_unstable() argument
231 clocksource_mark_unstable(struct clocksource * cs) clocksource_mark_unstable() argument
253 cs_watchdog_read(struct clocksource * cs,u64 * csnow,u64 * wdnow) cs_watchdog_read() argument
357 struct clocksource *cs = (struct clocksource *)csin; clocksource_verify_one_cpu() local
362 clocksource_verify_percpu(struct clocksource * cs) clocksource_verify_percpu() argument
421 struct clocksource *cs; clocksource_reset_watchdog() local
433 struct clocksource *cs; clocksource_watchdog() local
627 clocksource_enqueue_watchdog(struct clocksource * cs) clocksource_enqueue_watchdog() argument
644 struct clocksource *cs, *old_wd; clocksource_select_watchdog() local
679 clocksource_dequeue_watchdog(struct clocksource * cs) clocksource_dequeue_watchdog() argument
693 struct clocksource *cs, *tmp; __clocksource_watchdog_kthread() local
731 clocksource_is_watchdog(struct clocksource * cs) clocksource_is_watchdog() argument
738 clocksource_enqueue_watchdog(struct clocksource * cs) clocksource_enqueue_watchdog() argument
745 clocksource_dequeue_watchdog(struct clocksource * cs) clocksource_dequeue_watchdog() argument
748 clocksource_is_watchdog(struct clocksource * cs) clocksource_is_watchdog() argument
749 clocksource_mark_unstable(struct clocksource * cs) clocksource_mark_unstable() argument
756 clocksource_is_suspend(struct clocksource * cs) clocksource_is_suspend() argument
761 __clocksource_suspend_select(struct clocksource * cs) __clocksource_suspend_select() argument
790 struct clocksource *cs, *old_suspend; clocksource_suspend_select() local
818 clocksource_start_suspend_timing(struct clocksource * cs,u64 start_cycles) clocksource_start_suspend_timing() argument
856 clocksource_stop_suspend_timing(struct clocksource * cs,u64 cycle_now) clocksource_stop_suspend_timing() argument
891 struct clocksource *cs; clocksource_suspend() local
903 struct clocksource *cs; clocksource_resume() local
929 clocksource_max_adjustment(struct clocksource * cs) clocksource_max_adjustment() argument
955 clocks_calc_max_nsecs(u32 mult,u32 shift,u32 maxadj,u64 mask,u64 * max_cyc) clocks_calc_max_nsecs() argument
990 clocksource_update_max_deferment(struct clocksource * cs) clocksource_update_max_deferment() argument
1008 struct clocksource *cs; clocksource_find_best() local
1031 struct clocksource *best, *cs; __clocksource_select() local
1122 clocksource_enqueue(struct clocksource * cs) clocksource_enqueue() argument
1148 __clocksource_update_freq_scale(struct clocksource * cs,u32 scale,u32 freq) __clocksource_update_freq_scale() argument
1240 __clocksource_register_scale(struct clocksource * cs,u32 scale,u32 freq) __clocksource_register_scale() argument
1277 clocksource_unbind(struct clocksource * cs) clocksource_unbind() argument
1316 clocksource_unregister(struct clocksource * cs) clocksource_unregister() argument
1408 struct clocksource *cs; unbind_clocksource_store() local
[all...]
/linux/drivers/gpio/
H A Dgpio-spear-spics.c1 // SPDX-License-Identifier: GPL-2.0-only
21 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
31 * struct spear_spics - represents spi chip select control
34 * @sw_enable_bit: bit to enable s/w control over chipselects
36 * @cs_enable_mask: mask to select bits required to select chipselect
38 * @use_count: use count of a spi controller cs lines
61 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value()
62 if (spics->last_off != offset) { in spics_set_value()
63 spics->last_off = offset; in spics_set_value()
64 tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift); in spics_set_value()
[all …]
/linux/arch/m68k/include/asm/
H A Dm525xsim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
41 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
55 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
56 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
57 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
58 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
59 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
60 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
61 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
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/linux/arch/arm/mach-footbridge/
H A Ddc21285-timer.c1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/arm/mach-footbridge/dc21285-timer.c
23 static u64 cksrc_dc21285_read(struct clocksource *cs) in cksrc_dc21285_read() argument
25 return cs->mask - *CSR_TIMER2_VALUE; in cksrc_dc21285_read()
28 static int cksrc_dc21285_enable(struct clocksource *cs) in cksrc_dc21285_enable() argument
30 *CSR_TIMER2_LOAD = cs->mask; in cksrc_dc21285_enable()
36 static void cksrc_dc21285_disable(struct clocksource *cs) in cksrc_dc21285_disable() argument
45 .enable = cksrc_dc21285_enable,
47 .mask = CLOCKSOURCE_MASK(24),
95 /* Stop the timer if in one-shot mode */ in timer1_interrupt()
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/linux/arch/arm/plat-orion/
H A Dpcie.c2 * arch/arm/plat-orion/pcie.c
16 #include <plat/addr-map.h>
28 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
98 * MV-S104860-U0, Rev. C: in orion_pcie_reset()
101 * This bit should be cleared after the link is re-established. in orion_pcie_reset()
120 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
121 * WIN[0-3] -> DRAM bank[0-3]
154 for (i = 0; i < dram->num_cs; i++) { in orion_pcie_setup_wins()
155 const struct mbus_dram_window *cs = dram->cs + i; in orion_pcie_setup_wins() local
157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
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/linux/arch/x86/xen/
H A Dxen-asm.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Asm versions of Xen pv-ops, suitable for direct use.
10 #include <asm/asm-offsets.h>
12 #include <asm/processor-flags.h>
50 * Disabling events is simply a matter of making the event mask
51 * non-zero.
89 * Enable events. This clears the event mask and tests the pending
116 * (xen_)save_fl is used to get the current interrupt enable status.
122 * x86 use opposite senses (mask vs enable).
202 .fill xen_early_idt_handler_array + i*XEN_EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
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/linux/drivers/bus/
H A Dintel-ixp4xx-eb.c1 // SPDX-License-Identifier: GPL-2.0-only
32 /* Bits inside each CS timing register */
87 u32 mask; member
93 .prop = "intel,ixp4xx-eb-t1",
95 .mask = IXP4XX_EXP_T1_MASK,
99 .prop = "intel,ixp4xx-eb-t2",
101 .mask = IXP4XX_EXP_T2_MASK,
105 .prop = "intel,ixp4xx-eb-t3",
107 .mask = IXP4XX_EXP_T3_MASK,
111 .prop = "intel,ixp4xx-eb-t4",
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/linux/drivers/spi/
H A Dspi-fsl-espi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #define ESPI_SPIM 0x08 /* eSPI mask register */
39 /* eSPI Controller CS mode register definitions */
118 return ioread32be(espi->reg_base + offset); in fsl_espi_read_reg()
123 return ioread16be(espi->reg_base + offset); in fsl_espi_read_reg16()
128 return ioread8(espi->reg_base + offset); in fsl_espi_read_reg8()
134 iowrite32be(val, espi->reg_base + offset); in fsl_espi_write_reg()
140 iowrite16be(val, espi->reg_base + offset); in fsl_espi_write_reg16()
146 iowrite8(val, espi->reg_base + offset); in fsl_espi_write_reg8()
151 struct fsl_espi *espi = spi_controller_get_devdata(m->spi->controller); in fsl_espi_check_message()
[all …]
H A Dspi-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "spi-pxa2xx.h"
81 /* LPSS offset from drv_data->ioaddr */
83 /* Register offsets from drv_data->lpss_base or -1 */
106 .reg_capabilities = -1,
116 .reg_capabilities = -1,
126 .reg_capabilities = -1,
135 .reg_general = -1,
138 .reg_capabilities = -1,
145 .reg_general = -1,
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/linux/drivers/mtd/nand/raw/
H A Dau1550nd.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/mach-au1x00/au1000.h>
16 #include <asm/mach-au1x00/au1550nd.h>
23 int cs; member
33 * au_write_buf - write buffer to chip
48 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
54 * au_read_buf - read chip data into buffer
69 p[i] = readb(ctx->base + MEM_STNAND_DATA); in au_read_buf()
75 * au_write_buf16 - write buffer to chip
91 writew(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf16()
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/linux/kernel/cgroup/
H A Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
24 #include "cpuset-internal.h"
49 * node binding, add this key to provide a quick low-cost judgment
63 [PERR_ACCESS] = "Enable partition not permitted",
73 * Exclusive CPUs distributed out to local or remote sub-partitions of
95 * - update_partition_sd_lb()
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/linux/sound/soc/codecs/
H A Dwcd-mbhc-v2.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
14 #include "wcd-mbhc-v2.h"
76 /* Holds type of Headset - Mono/Stereo */
78 /* Holds mbhc detection method - ADC/Legacy */
85 if (!mbhc->fields[field].reg) in wcd_mbhc_write_field()
88 return snd_soc_component_write_field(mbhc->component, in wcd_mbhc_write_field()
89 mbhc->fields[field].reg, in wcd_mbhc_write_field()
90 mbhc->fields[field].mask, val); in wcd_mbhc_write_field()
95 if (!mbhc->fields[field].reg) in wcd_mbhc_read_field()
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/linux/sound/soc/kirkwood/
H A Dkirkwood-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * kirkwood-dma.c
6 * (c) 2010 Arnaud Patard <arnaud.patard@rtp-net.org>
15 #include <linux/dma-mapping.h>
44 unsigned long mask, status, cause; in kirkwood_dma_irq() local
46 mask = readl(priv->io + KIRKWOOD_INT_MASK); in kirkwood_dma_irq()
47 status = readl(priv->io + KIRKWOOD_INT_CAUSE) & mask; in kirkwood_dma_irq()
49 cause = readl(priv->io + KIRKWOOD_ERR_CAUSE); in kirkwood_dma_irq()
53 writel(cause, priv->io + KIRKWOOD_ERR_CAUSE); in kirkwood_dma_irq()
65 writel(status, priv->io + KIRKWOOD_INT_CAUSE); in kirkwood_dma_irq()
[all …]
/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
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/linux/arch/mips/kernel/
H A Dcsrc-sb1250.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 return SB1250_HPT_VALUE - count; in sb1250_hpt_get_cycles()
35 static u64 sb1250_hpt_read(struct clocksource *cs) in sb1250_hpt_read() argument
41 .name = "bcm1250-counter-3",
44 .mask = CLOCKSOURCE_MASK(23),
55 struct clocksource *cs = &bcm1250_clocksource; in sb1250_clocksource_init() local
57 /* Setup hpt using timer #3 but do not enable irq for it */ in sb1250_clocksource_init()
68 clocksource_register_hz(cs, V_SCD_TIMER_FREQ); in sb1250_clocksource_init()
/linux/drivers/edac/
H A Damd64_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * cleared to prevent re-enabling the hardware by this driver.
21 if (!pvt->flags.zn_regs_v2) in get_umc_reg()
33 /* Per-node stuff */
41 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
83 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
96 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
108 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg); in f15h_select_dct()
109 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
111 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
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