/linux/Documentation/devicetree/bindings/mfd/ |
H A D | google,cros-ec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Benson Leung <bleung@chromium.org> 11 - Guenter Roeck <groeck@chromium.org> 14 Google's ChromeOS EC is a microcontroller which talks to the AP and 16 The EC can be connected through various interfaces (I2C, SPI, and others) 22 - description: 23 For implementations of the EC connected through I2C. [all …]
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/linux/Documentation/devicetree/bindings/extcon/ |
H A D | extcon-usbc-cros-ec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/extcon/extcon-usbc-cros-ec.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ChromeOS EC USB Type-C cable and accessories detection 10 - Benson Leung <bleung@chromium.org> 16 The node for this device must be under a cros-ec node like google,cros-ec-spi 17 or google,cros-ec-i2c. 21 const: google,extcon-usbc-cros-ec 23 google,usb-port-id: [all …]
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/linux/Documentation/devicetree/bindings/chrome/ |
H A D | google,cros-ec-typec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Google Chrome OS EC(Embedded Controller) Type C port driver. 10 - Benson Leung <bleung@chromium.org> 11 - Prashant Malani <pmalani@chromium.org> 14 Chrome OS devices have an Embedded Controller(EC) which has access to 17 cros-ec node like google,cros-ec-spi. 21 const: google,cros-ec-typec [all …]
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H A D | google,cros-kbd-led-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/chrome/google,cros-kbd-led-backlight.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Tzung-Bi Shih <tzungbi@kernel.org> 14 const: google,cros-kbd-led-backlight 17 - compatible 22 - | 23 spi { 24 #address-cells = <1>; [all …]
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/linux/Documentation/devicetree/bindings/pwm/ |
H A D | google,cros-ec-pwm.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/pwm/google,cros-ec-pwm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: PWM controlled by ChromeOS EC 10 - Thierry Reding <thierry.reding@gmail.com> 11 - '"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>' 14 Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller 15 (EC) and controlled via a host-command interface. 16 An EC PWM node should be only found as a sub-node of the EC node (see [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | sc7280-idp-ec-h1.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * sc7280 EC/H1 over SPI (common between IDP2 and CRD) 11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>; 12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; 14 cros_ec: ec@0 { 15 compatible = "google,cros-ec-spi"; 17 interrupt-parent = <&tlmm>; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&ap_ec_int_l>; 21 spi-max-frequency = <3000000>; [all …]
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H A D | sc7280-herobrine.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 16 #include <dt-bindings/input/gpio-keys.h> 17 #include <dt-bindings/input/input.h> 18 #include <dt-bindings/leds/common.h> 20 #include "sc7280-qcard.dtsi" 21 #include "sc7280-chrome-common.dtsi" 25 stdout-path = "serial0:115200n8"; 38 ppvar_sys: ppvar-sys-regulator { 39 compatible = "regulator-fixed"; 40 regulator-name = "ppvar_sys"; [all …]
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H A D | sc7180-trogdor.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/gpio-keys.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/leds/common.h> 12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 13 #include <dt-bindings/sound/sc7180-lpass.h> 16 #include "sc7180-firmware-tfa.dtsi" 22 thermal-zones { 23 charger_thermal: charger-thermal { [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | google,cros-ec-codec.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/sound/google,cros-ec-codec.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Audio codec controlled by ChromeOS EC 10 - Cheng-Yi Chiang <cychiang@chromium.org> 11 - Tzung-Bi Shih <tzungbi@kernel.org> 14 Google's ChromeOS EC codec is a digital mic codec provided by the 15 Embedded Controller (EC) and is controlled via a host-command 16 interface. An EC codec node should only be found inside the "codecs" [all …]
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/linux/Documentation/devicetree/bindings/regulator/ |
H A D | google,cros-ec-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/regulator/google,cros-ec-regulator.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ChromeOS EC controlled voltage regulators 10 - Pi-Hsun Shih <pihsun@chromium.org> 17 - $ref: regulator.yaml# 21 const: google,cros-ec-regulator 25 description: Identifier for the voltage regulator to ChromeOS EC. 28 - compatible [all …]
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/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt8183-kukui.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 21 stdout-path = "serial0:115200n8"; 25 compatible = "pwm-backlight"; 27 power-supply = <®_vsys>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; [all …]
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H A D | mt8195-cherry.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/spmi/spmi.h> 25 backlight_lcd0: backlight-lcd0 { 26 compatible = "pwm-backlight"; 27 brightness-levels = <0 1023>; 28 default-brightness-level = <576>; 29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>; 30 num-interpolated-steps = <1023>; 32 power-supply = <&ppvar_sys>; [all …]
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H A D | mt8186-corsola.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 /dts-v1/; 7 #include <dt-bindings/pinctrl/mt8186-pinfunc.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/gpio-keys.h> 11 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h> 26 stdout-path = "serial0:115200n8"; 35 backlight_lcd0: backlight-lcd0 { 36 compatible = "pwm-backlight"; [all …]
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H A D | mt8173-elm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/input/linux-event-codes.h> 8 #include <dt-bindings/regulator/dlg,da9211-regulator.h> 9 #include <dt-bindings/gpio/gpio.h> 25 compatible = "pwm-backlight"; 27 power-supply = <&bl_fixed_reg>; 28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&panel_backlight_en_pins>; [all …]
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/linux/drivers/platform/chrome/ |
H A D | cros_ec_spi.c | 1 // SPDX-License-Identifier: GPL-2.0 2 // SPI interface for ChromeOS Embedded Controller 14 #include <linux/spi/spi.h> 23 * Number of EC preamble bytes we read at a time. Since it takes 24 * about 400-500us for the EC to respond there is not a lot of 25 * point in tuning this. If the EC could respond faster then 28 * SPI transfer size is 256 bytes, so at 5MHz we need a response 34 * Allow for a long time for the EC to respond. We support i2c 50 * for this, clocking in at 2-3ms. 55 * Time between raising the SPI chip select (for the end of a [all …]
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H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 26 If you have an ACPI-compatible Chromebook, say Y or M here. 47 The range of memory used is 0xf00000-0x1000000, traditionally 73 devices that have multiple drop-in options for one component. 81 Controller (EC) providing keyboard, battery and power services. 83 protocol for talking to the EC is defined by the bus driver. 94 EC through an I2C bus. This uses a simple byte-level protocol with 102 If you say Y here, you get support for talking to the ChromeOS EC 103 through rpmsg. This uses a simple byte-level protocol with a 104 checksum. Also since there's no addition EC-to-host interrupt, this [all …]
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/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3399-gru.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Copyright 2016-2017 Google, Inc 8 #include <dt-bindings/input/input.h> 9 #include "rk3399-op1.dtsi" 18 stdout-path = "serial2:115200n8"; 27 * - Rails that only connect to the EC (or devices that the EC talks to) 29 * - Rails _are_ included if the rails go to the AP even if the AP 38 * - The EC controls the enable and the EC always enables a rail as 40 * - The rails are actually connected to each other by a jumper and 45 ppvar_sys: regulator-ppvar-sys { [all …]
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/linux/drivers/gpio/ |
H A D | gpio-cros-ec.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * This driver provides the ability to control GPIOs on the Chrome OS EC. 23 /* Prefix all names to avoid collisions with EC <-> AP nets */ 24 static const char cros_ec_gpio_prefix[] = "EC:"; 29 const char *name = gc->names[gpio] + strlen(cros_ec_gpio_prefix); in cros_ec_gpio_set() 44 dev_err(gc->parent, "error setting gpio%d (%s) on EC: %d\n", gpio, name, ret); in cros_ec_gpio_set() 49 const char *name = gc->names[gpio] + strlen(cros_ec_gpio_prefix); in cros_ec_gpio_get() 58 return -EINVAL; in cros_ec_gpio_get() 63 dev_err(gc->parent, "error getting gpio%d (%s) on EC: %d\n", gpio, name, ret); in cros_ec_gpio_get() 75 const char *name = gc->names[gpio] + strlen(cros_ec_gpio_prefix); in cros_ec_gpio_get_direction() [all …]
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/linux/include/linux/platform_data/ |
H A D | cros_ec_proto.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 29 * The EC is unresponsive for a time after a reboot command. Add a 35 * Max bus-specific overhead incurred by request/responses. 38 * SPI requires up to 32 additional bytes for responses. 45 * EC panic is not covered by the standard (0-F) ACPI notify values. 46 * Arbitrarily choosing B0 to notify ec panic, which is in the 84-BF 52 * Command interface between EC and AP, for LPC, I2C and SPI interfaces. 69 * struct cros_ec_command - Information about a ChromeOS EC command. 73 * @insize: Max number of bytes to accept from the EC. 74 * @result: EC's response to the command (separate from communication failure). [all …]
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/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra124-nyan.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/thermal/thermal.h> 14 stdout-path = "serial0:115200n8"; 20 * missing a unit-address. However, the bootloader on these Chromebook 22 * Adding the unit-address causes the bootloader to create a /memory 34 /delete-node/ memory@80000000; 40 vdd-supply = <&vdd_3v3_hdmi>; 41 pll-supply = <&vdd_hdmi_pll>; 42 hdmi-supply = <&vdd_5v0_hdmi>; [all …]
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H A D | tegra124-venice2.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 18 stdout-path = "serial0:115200n8"; 29 vdd-supply = <&vdd_3v3_hdmi>; 30 pll-supply = <&vdd_hdmi_pll>; 31 hdmi-supply = <&vdd_5v0_hdmi>; 33 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 34 nvidia,hpd-gpio = 41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; [all …]
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/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5420-peach-pit.dts | 1 // SPDX-License-Identifier: GPL-2.0 8 /dts-v1/; 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/clock/maxim,max77802.h> 13 #include <dt-bindings/regulator/maxim,max77802.h> 14 #include <dt-bindings/sound/samsung-i2s.h> 16 #include "exynos5420-cpus.dtsi" 21 compatible = "google,pit-rev16", [all …]
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H A D | exynos5800-peach-pi.dts | 1 // SPDX-License-Identifier: GPL-2.0 8 /dts-v1/; 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/clock/maxim,max77802.h> 13 #include <dt-bindings/regulator/maxim,max77802.h> 14 #include <dt-bindings/sound/samsung-i2s.h> 16 #include "exynos5420-cpus.dtsi" 21 compatible = "google,pi-rev16", [all …]
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/linux/drivers/input/keyboard/ |
H A D | cros_ec_keyb.c | 1 // SPDX-License-Identifier: GPL-2.0 2 // ChromeOS EC keyboard driver 6 // This driver uses the ChromeOS EC byte-level message-based protocol for 7 // communicating the keyboard state (which keys are pressed) from a keyboard EC 8 // to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing, 10 // motivation for this is to keep the EC firmware as simple as possible, since 11 // it cannot be easily upgraded and EC flash/IRAM space is relatively 19 #include <linux/input/vivaldi-fmap.h> 33 * struct cros_ec_keyb - Structure representing EC keyboard device 38 * @ghost_filter: true to enable the matrix key-ghosting filter [all …]
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/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra132-norrin.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 18 stdout-path = "serial0:115200n8"; 30 vdd-supply = <&vdd_3v3_hdmi>; 31 pll-supply = <&vdd_hdmi_pll>; 32 hdmi-supply = <&vdd_5v0_hdmi>; 34 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 35 nvidia,hpd-gpio = 42 avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; [all …]
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