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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi126 crg: clock-reset-controller@8a22000 { label
127 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
160 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
161 resets = <&crg 0xbc 4>;
168 resets = <&crg 0xbc 8>;
174 resets = <&crg 0xbc 9>;
181 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
182 resets = <&crg 0xbc 6>;
189 resets = <&crg 0xbc 10>;
197 clocks = <&crg HISTB_COMBPHY0_CLK>;
[all …]
/linux/drivers/clk/hisilicon/
H A Dcrg-hi3516cv300.c14 #include "crg.h"
17 /* hi3516CV300 core CRG */
175 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); in hi3516cv300_clk_unregister() local
180 ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data); in hi3516cv300_clk_unregister()
182 ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data); in hi3516cv300_clk_unregister()
184 ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data); in hi3516cv300_clk_unregister()
192 /* hi3516CV300 sysctrl CRG */
234 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); in hi3516cv300_sysctrl_clk_unregister() local
240 crg->clk_data); in hi3516cv300_sysctrl_clk_unregister()
250 .compatible = "hisilicon,hi3516cv300-crg",
[all …]
H A Dcrg-hi3798cv200.c14 #include "crg.h"
17 /* hi3798CV200 core CRG */
256 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); in hi3798cv200_clk_unregister() local
262 crg->clk_data); in hi3798cv200_clk_unregister()
265 crg->clk_data); in hi3798cv200_clk_unregister()
268 crg->clk_data); in hi3798cv200_clk_unregister()
276 /* hi3798CV200 sysctrl CRG */
321 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); in hi3798cv200_sysctrl_clk_unregister() local
327 crg->clk_data); in hi3798cv200_sysctrl_clk_unregister()
336 { .compatible = "hisilicon,hi3798cv200-crg",
[all …]
H A Dclk-hi3519.c128 struct hi3519_crg_data *crg = platform_get_drvdata(pdev); in hi3519_clk_unregister() local
134 crg->clk_data); in hi3519_clk_unregister()
137 crg->clk_data); in hi3519_clk_unregister()
140 crg->clk_data); in hi3519_clk_unregister()
145 struct hi3519_crg_data *crg; in hi3519_clk_probe() local
147 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); in hi3519_clk_probe()
148 if (!crg) in hi3519_clk_probe()
151 crg->rstc = hisi_reset_init(pdev); in hi3519_clk_probe()
152 if (!crg->rstc) in hi3519_clk_probe()
155 crg->clk_data = hi3519_clk_register(pdev); in hi3519_clk_probe()
[all …]
H A Dclk-hi3559a.c19 #include "crg.h"
551 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); in hi3559av100_clk_unregister() local
556 ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data); in hi3559av100_clk_unregister()
558 ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data); in hi3559av100_clk_unregister()
560 ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data); in hi3559av100_clk_unregister()
752 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); in hi3559av100_shub_clk_unregister() local
757 ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data); in hi3559av100_shub_clk_unregister()
759 ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data); in hi3559av100_shub_clk_unregister()
761 ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data); in hi3559av100_shub_clk_unregister()
763 ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data); in hi3559av100_shub_clk_unregister()
[all …]
H A DMakefile11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
16 obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3519.dtsi37 crg: clock-reset-controller@12010000 { label
38 compatible = "hisilicon,hi3519-crg";
55 clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
64 clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
73 clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
82 clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;
91 clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;
130 clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
142 clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
154 clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
/linux/Documentation/devicetree/bindings/clock/
H A Dhisi-crg.txt1 * HiSilicon Clock and Reset Generator(CRG)
3 The CRG module provides clock and reset signals to various
13 - "hisilicon,hi3516cv300-crg"
15 - "hisilicon,hi3519-crg"
16 - "hisilicon,hi3798cv200-crg"
31 A reset signal can be controlled by writing a bit register in the CRG module.
36 Example: CRG nodes
37 CRG: clock-reset-controller@12010000 {
38 compatible = "hisilicon,hi3519-crg";
48 clocks = <&CRG HI3519_I2C0_RST>;
[all …]
H A Dstarfive,jh7110-voutcrg.yaml44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
70 #include <dt-bindings/clock/starfive,jh7110-crg.h>
72 #include <dt-bindings/reset/starfive,jh7110-crg.h>
H A Dstarfive,jh7110-ispcrg.yaml42 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
47 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
68 #include <dt-bindings/clock/starfive,jh7110-crg.h>
70 #include <dt-bindings/reset/starfive,jh7110-crg.h>
H A Dstarfive,jh7110-stgcrg.yaml44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
63 #include <dt-bindings/clock/starfive,jh7110-crg.h>
H A Dstarfive,jh7110-aoncrg.yaml71 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
76 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
90 #include <dt-bindings/clock/starfive,jh7110-crg.h>
H A Dhi3670-clock.txt16 - "hisilicon,hi3670-media1-crg"
17 - "hisilicon,hi3670-media2-crg"
H A Dstarfive,jh7110-syscrg.yaml82 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
87 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
/linux/Documentation/devicetree/bindings/mmc/
H A Dhisilicon,hi3798cv200-dw-mshc.yaml42 It is integrated into CRG core on the SoC and has to be controlled during tuning.
44 - description: A phandle pointed to the CRG syscon node
45 - description: Sample DLL register offset in CRG address space
80 clocks = <&crg HISTB_MMC_CIU_CLK>,
81 <&crg HISTB_MMC_BIU_CLK>,
82 <&crg HISTB_MMC_SAMPLE_CLK>,
83 <&crg HISTB_MMC_DRV_CLK>;
85 resets = <&crg 0xa0 4>;
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-hisi-inno-usb2.txt39 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
40 resets = <&crg 0xbc 4>;
47 resets = <&crg 0xbc 8>;
53 resets = <&crg 0xbc 9>;
60 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
61 resets = <&crg 0xbc 6>;
68 resets = <&crg 0xbc 10>;
/linux/Documentation/devicetree/bindings/pci/
H A Dhisilicon-histb-pcie.txt60 clocks = <&crg PCIE_AUX_CLK>,
61 <&crg PCIE_PIPE_CLK>,
62 <&crg PCIE_SYS_CLK>,
63 <&crg PCIE_BUS_CLK>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h81 * Note: Tsi148 Register Group (CRG) consists of the following
91 * Command/Status Registers (CRG + $004)
371 * Inbound Translation CRG
380 * CRG
488 * GCSR CRG
501 * GCSR CRG
519 * CR/CSR CRG
553 * Revision ID/Class Code Registers (CRG +$008)
561 * Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C)
568 * Memory Base Address Lower Reg (CRG + $010)
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dhisilicon,histb-xhci.txt36 clocks = <&crg HISTB_USB3_BUS_CLK>,
37 <&crg HISTB_USB3_UTMI_CLK>,
38 <&crg HISTB_USB3_PIPE_CLK>,
39 <&crg HISTB_USB3_SUSPEND_CLK>;
41 resets = <&crg 0xb0 12>;
/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hix5hd2-gmac.txt51 clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;
53 resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>;
H A Dhisilicon-femac.txt34 clocks = <&crg HI3518EV200_ETH_CLK>;
35 resets = <&crg 0xec 0>,<&crg 0xec 3>;
H A Dhisilicon-femac-mdio.txt15 clocks = <&crg HI3516CV300_MDIO_CLK>;
/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dhi3798cv200-perictrl.yaml57 clocks = <&crg 42>;
58 resets = <&crg 0x188 4>;
59 assigned-clocks = <&crg 42>;
/linux/include/dt-bindings/clock/
H A Dhi3516cv300-clock.h9 /* hi3516CV300 core CRG */
33 /* hi3516CV300 sysctrl CRG */
H A Dhistb-clock.h9 /* clocks provided by core CRG */
62 /* clocks provided by mcu CRG */

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