Searched full:cpuclk (Results 1 – 18 of 18) sorted by relevance
| /linux/drivers/clk/mvebu/ |
| H A D | clk-cpu.c | 51 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_recalc_rate() local
54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; in clk_cpu_recalc_rate()
78 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_off_set_rate() local
83 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_off_set_rate()
84 & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8)))) in clk_cpu_off_set_rate()
85 | (div << (cpuclk->cpu * 8)); in clk_cpu_off_set_rate()
86 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_off_set_rate()
88 reload_mask = 1 << (20 + cpuclk->cpu); in clk_cpu_off_set_rate()
90 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate()
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| H A D | common.c | 111 const char *cpuclk_name = "cpuclk"; in mvebu_coreclk_setup()
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| H A D | kirkwood.c | 261 "cpuclk",
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| /linux/arch/mips/txx9/generic/ |
| H A D | setup_tx4927.c | 92 unsigned int cpuclk = 0; in tx4927_setup() local
126 cpuclk = txx9_gbus_clock * 2; break; in tx4927_setup()
129 cpuclk = txx9_gbus_clock * 5 / 2; break; in tx4927_setup()
132 cpuclk = txx9_gbus_clock * 3; break; in tx4927_setup()
135 cpuclk = txx9_gbus_clock * 4; break; in tx4927_setup()
137 txx9_cpu_clock = cpuclk; in tx4927_setup()
142 cpuclk = txx9_cpu_clock; in tx4927_setup()
147 txx9_gbus_clock = cpuclk / 2; break; in tx4927_setup()
150 txx9_gbus_clock = cpuclk * 2 / 5; break; in tx4927_setup()
153 txx9_gbus_clock = cpuclk / 3; break; in tx4927_setup()
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| H A D | setup_tx4938.c | 97 unsigned int cpuclk = 0; in tx4938_setup() local
132 cpuclk = txx9_gbus_clock * 2; break; in tx4938_setup()
135 cpuclk = txx9_gbus_clock * 5 / 2; break; in tx4938_setup()
138 cpuclk = txx9_gbus_clock * 3; break; in tx4938_setup()
141 cpuclk = txx9_gbus_clock * 4; break; in tx4938_setup()
144 cpuclk = txx9_gbus_clock * 9 / 2; break; in tx4938_setup()
146 txx9_cpu_clock = cpuclk; in tx4938_setup()
151 cpuclk = txx9_cpu_clock; in tx4938_setup()
156 txx9_gbus_clock = cpuclk / 2; break; in tx4938_setup()
159 txx9_gbus_clock = cpuclk * 2 / 5; break; in tx4938_setup()
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| /linux/arch/mips/cavium-octeon/ |
| H A D | oct_ilm.c | 33 u64 cpuclk, avg, max, min; in oct_ilm_show() local
36 cpuclk = octeon_get_clock_rate(); in oct_ilm_show()
38 max = (curr_li.max_latency * 1000000000) / cpuclk; in oct_ilm_show()
39 min = (curr_li.min_latency * 1000000000) / cpuclk; in oct_ilm_show()
40 avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt); in oct_ilm_show()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-cpu-8996.c | 277 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); in clk_cpu_8996_pmux_get_parent() local
280 regmap_read(clkr->regmap, cpuclk->reg, &val); in clk_cpu_8996_pmux_get_parent()
288 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); in clk_cpu_8996_pmux_set_parent() local
293 return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val); in clk_cpu_8996_pmux_set_parent()
549 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb); in cpu_clk_notifier_cb() local
554 qcom_cpu_clk_msm8996_acd_init(cpuclk->clkr.regmap); in cpu_clk_notifier_cb()
566 clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, SMUX_INDEX); in cpu_clk_notifier_cb()
573 clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ACD_INDEX); in cpu_clk_notifier_cb()
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-xp-mv78460.dtsi | 35 clocks = <&cpuclk 0>;
43 clocks = <&cpuclk 1>;
51 clocks = <&cpuclk 2>;
59 clocks = <&cpuclk 3>;
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| H A D | armada-xp-98dx3336.dtsi | 22 clocks = <&cpuclk 1>;
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| H A D | armada-xp-98dx4251.dtsi | 22 clocks = <&cpuclk 1>;
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| H A D | armada-xp-98dx3236.dtsi | 35 clocks = <&cpuclk 0>;
158 cpuclk: clock-complex@18700 { label
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| H A D | armada-xp-mv78230.dtsi | 33 clocks = <&cpuclk 0>;
41 clocks = <&cpuclk 1>;
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| H A D | armada-xp-mv78260.dtsi | 34 clocks = <&cpuclk 0>;
42 clocks = <&cpuclk 1>;
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| H A D | armada-xp.dtsi | 102 cpuclk: clock-complex@18700 { label
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| /linux/arch/arm/boot/dts/sigmastar/ |
| H A D | mstar-infinity2m.dtsi | 30 clock-names = "cpuclk";
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| H A D | mstar-v7.dtsi | 25 clock-names = "cpuclk";
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| /linux/drivers/clk/berlin/ |
| H A D | bg2q.c | 359 /* cpuclk divider is fixed to 1 */ in berlin2q_clock_setup()
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| /linux/drivers/video/fbdev/aty/ |
| H A D | radeon_base.c | 1377 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
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