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/linux/tools/memory-model/Documentation/
H A Dlocking.txt27 void CPU0(void)
43 The basic rule guarantees that if CPU0() acquires mylock before CPU1(),
59 void CPU0(void)
75 This converse to the basic rule guarantees that if CPU0() acquires
94 void CPU0(void)
108 /* CPU1() is the exactly the same as CPU0(). */
119 void CPU0(void)
133 /* CPU1() is the exactly the same as CPU0(). */
155 void CPU0(void)
188 void CPU0(void)
[all …]
H A Drecipes.txt73 void CPU0(void)
89 The basic rule guarantees that if CPU0() acquires mylock before CPU1(),
99 void CPU0(void)
115 This converse to the basic rule guarantees that if CPU0() acquires
130 void CPU0(void)
163 void CPU0(void)
220 void CPU0(void)
255 void CPU0(void)
296 void CPU0(void)
364 void CPU0(void)
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroidhc1.dts33 cpu0_thermal: cpu0-thermal {
61 cooling-device = <&cpu0 0 2>,
77 cooling-device = <&cpu0 3 8>,
110 cooling-device = <&cpu0 0 2>,
121 cooling-device = <&cpu0 3 8>,
154 cooling-device = <&cpu0 0 2>,
165 cooling-device = <&cpu0 3 8>,
198 cooling-device = <&cpu0 0 2>,
209 cooling-device = <&cpu0 3 8>,
H A Dexynos5420-arndale-octa.dts68 &cpu0 {
107 cooling-device = <&cpu0 0 2>,
123 cooling-device = <&cpu0 3 6>,
139 cooling-device = <&cpu0 6 11>,
178 cooling-device = <&cpu0 0 2>,
190 cooling-device = <&cpu0 3 6>,
202 cooling-device = <&cpu0 6 11>,
241 cooling-device = <&cpu0 0 2>,
253 cooling-device = <&cpu0 3 6>,
265 cooling-device = <&cpu0 6 11>,
[all …]
H A Dexynos5422-odroidxu3-lite.dts52 cooling-device = <&cpu0 3 7>,
63 cooling-device = <&cpu0 3 7>,
74 cooling-device = <&cpu0 3 7>,
85 cooling-device = <&cpu0 3 7>,
H A Dexynos5422-odroidxu3-common.dtsi56 cpu0_thermal: cpu0-thermal {
112 cooling-device = <&cpu0 0 2>,
128 cooling-device = <&cpu0 3 8>,
190 cooling-device = <&cpu0 0 2>,
201 cooling-device = <&cpu0 3 8>,
263 cooling-device = <&cpu0 0 2>,
274 cooling-device = <&cpu0 3 8>,
336 cooling-device = <&cpu0 0 2>,
347 cooling-device = <&cpu0 3 8>,
/linux/Documentation/translations/zh_CN/scheduler/
H A Dsched-capacity.rst61 - work_per_hz(CPU0) = W
67 - capacity(CPU0) = C
74 CPU0 work ^
93 - max_freq(CPU0) = F
98 - capacity(CPU0) = C
103 CPU0 work ^
174 - capacity(CPU0) = C
179 CPU0 work ^
336 capacity(CPU0) = C
339 workload on CPU0
H A Dsched-energy.rst152 CPU0 CPU1 CPU2 CPU3
167 768 ============= * CPU0: 200 / 341 * 150 = 88
177 CPU0 CPU1 CPU2 CPU3
185 768 ============= * CPU0: 200 / 341 * 150 = 88
195 CPU0 CPU1 CPU2 CPU3
197 **情况3. P依旧留在prev_cpu/CPU0**::
202 768 ============= * CPU0: 400 / 512 * 300 = 234
212 CPU0 CPU1 CPU2 CPU3
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-opp-zaius.dts313 /* CPU0 PRM 0.7V */
314 /* CPU0 PRM 1.2V CH03 */
315 /* CPU0 PRM 0.8V */
316 /* CPU0 PRM 1.2V CH47 */
372 /* Master selector PCA9541A @70h (other master: CPU0)
393 /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
394 /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
395 /* CPU0 VR ISL68137 0.8V PMBUS @60h */
396 /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */
397 /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
[all …]
/linux/Documentation/scheduler/
H A Dsched-capacity.rst61 - work_per_hz(CPU0) = W
67 - capacity(CPU0) = C
70 To draw the parallel with Arm big.LITTLE, CPU0 would be a big while CPU1 would
76 CPU0 work ^
86 CPU0 has the highest capacity in the system (C), and completes a fixed amount of
88 CPU0, and thus only completes W/2 in T.
96 - max_freq(CPU0) = F
101 - capacity(CPU0) = C
107 CPU0 work ^
190 - capacity(CPU0) = C
[all …]
/linux/tools/virtio/virtio-trace/
H A DREADME63 -chardev pipe,id=charchannel1,path=/tmp/virtio-trace/trace-path-cpu0\
65 id=channel1,name=trace-path-cpu0\
77 <source path='/tmp/virtio-trace/trace-path-cpu0'/>
78 <target type='virtio' name='trace-path-cpu0'/>
83 example, if a guest use three CPUs, chardev names should be trace-path-cpu0,
107 # cat /tmp/virtio-trace/trace-path-cpu0.out
/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt42 1 = cpuclk (CPU0 clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
48 1 = cpuclk (CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
/linux/arch/arm64/boot/dts/renesas/
H A Dulcb-simple-audio-card.dtsi9 * (A) CPU0 <----> ak4613
27 * (A) CPU0 <-> ak4613
59 * (A) CPU0 <-> ak4613
80 * (A) CPU0 <-> ak4613
H A Dulcb-audio-graph-card.dtsi9 * (A) CPU0 <-----> ak4613
23 dais = <&snd_ulcb1 /* (A) CPU0 <-> ak4613 */
34 * (A) CPU0 <-> ak4613
66 * (A) CPU0 <-> ak4613
H A Dulcb-audio-graph-card-mix+split.dtsi12 * (A) CPU0 (2ch) <-----> (2ch) (X) ak4613 (MIX-0)
30 dais = <&snd_ulcb1 /* (A) CPU0 */
47 /* (A) CPU0 <-> (X) ak4613 */
70 * (A) CPU0
H A Dulcb-audio-graph-card2-mix+split.dtsi12 * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0)
29 links = <&fe_a /* (A) CPU0 */
44 * (A) CPU0 (MIX-0)
87 * (A) CPU0
/linux/Documentation/core-api/irq/
H A Dirq-affinity.rst21 Here is an example of restricting IRQ44 (eth1) to CPU0-3 then restricting
38 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
57 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
61 i.e counters for the CPU0-3 did not change.
/linux/tools/power/cpupower/bench/
H A Dcpufreq-bench_script.sh30 echo $up_threshold >/sys/devices/system/cpu/cpu0/cpufreq/ondemand/up_threshold
31 echo $sampling_rate >/sys/devices/system/cpu/cpu0/cpufreq/ondemand/sampling_rate
32 up_threshold_set=$(cat /sys/devices/system/cpu/cpu0/cpufreq/ondemand/up_threshold)
33 sampling_rate_set=$(cat /sys/devices/system/cpu/cpu0/cpufreq/ondemand/sampling_rate)
/linux/Documentation/devicetree/bindings/thermal/
H A Dthermal-cooling-devices.yaml59 // Example 1: Cpufreq cooling device on CPU0
64 CPU0: cpu@0 {
97 cpu0-thermal {
115 cooling-device = <&CPU0 5 5>;
/linux/Documentation/translations/zh_CN/cpu-freq/
H A Dcpufreq-stats.rst57 <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # ls -l
79 <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat time_in_state
93 <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat total_trans
107 <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat trans_table
/linux/Documentation/translations/zh_TW/cpu-freq/
H A Dcpufreq-stats.rst57 <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # ls -l
79 <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat time_in_state
93 <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat total_trans
107 <mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat trans_table
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b.dtsi19 cpu = <&cpu0>;
46 cpu0: cpu@0 { label
122 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
131 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
/linux/arch/arm/mach-omap2/
H A Domap-mpuss-lowpower.c10 * CPU0 and CPU1 LPRM modules.
11 * CPU0, CPU1 and MPUSS each have there own power domain and
14 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
23 * CPU0 CPU1 MPUSS
32 * Note: CPU0 is the master core and it is the last CPU to go down
115 * Program the wakeup routine address for the CPU0 and CPU1
388 pr_err("Lookup failed for CPU0 pwrdm\n"); in omap4_mpuss_init()
396 /* Initialise CPU0 power domain state to ON */ in omap4_mpuss_init()
H A Dcpuidle44xx.c128 * CPU0 has to wait and stay ON until CPU1 is OFF state. in omap_enter_idle_coupled()
239 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
247 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
257 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
276 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
284 /* C2 - CPU0 RET + CPU1 RET + MPU CSWR */
/linux/arch/riscv/include/asm/
H A Dmembarrier.h29 * to the mm for which a membarrier SYNC_CORE is done on CPU0: in membarrier_arch_switch_mm()
31 * - [CPU0] sets all bits in the mm icache_stale_mask (in in membarrier_arch_switch_mm()
36 * - [CPU0] loads rq->curr within membarrier and observes in membarrier_arch_switch_mm()

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