Home
last modified time | relevance | path

Searched +full:cpu0 +full:- +full:thermal (Results 1 – 25 of 143) sorted by relevance

123456

/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroidhc1.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include "exynos5422-odroid-core.dtsi"
16 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
19 led-controller {
20 compatible = "pwm-leds";
22 led-1 {
26 pwm-names = "pwm2";
27 max-brightness = <255>;
[all …]
H A Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&power_key>;
25 power-key {
36 debounce-interval = <0>;
[all …]
H A Dexynos5410.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
33 cpu0: cpu@0 { label
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
[all …]
H A Dexynos4412-prime.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 * non-Prime version. Therefore we need to update OPPs table and
12 * thermal maps accordingly.
16 /delete-property/turbo-mode;
20 opp-1600000000 {
21 opp-hz = /bits/ 64 <1600000000>;
22 opp-microvolt = <1350000>;
23 clock-latency-ns = <200000>;
25 opp-1704000000 {
26 opp-hz = /bits/ 64 <1704000000>;
[all …]
H A Dexynos5422-odroidxu3-lite.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3-Lite board device tree source
11 /dts-v1/;
12 #include "exynos5422-odroidxu3-common.dtsi"
13 #include "exynos5422-odroidxu3-audio.dtsi"
14 #include "exynos54xx-odroidxu-leds.dtsi"
18 compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5";
34 samsung,asv-bin = <2>;
38 * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies
40 * Therefore we need to update OPPs tables and thermal maps accordingly.
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dthermal-cooling-devices.yaml1 # SPDX-License-Identifier: (GPL-2.0)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-cooling-devices.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Thermal cooling device
11 - Amit Kucheria <amitk@kernel.org>
14 Thermal management is achieved in devicetree by describing the sensor hardware
15 and the software abstraction of cooling devices and thermal zones required to
16 take appropriate action to mitigate thermal overload.
18 The following node types are used to completely describe a thermal management
[all …]
H A Dthermal-zones.yaml1 # SPDX-License-Identifier: (GPL-2.0)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-zones.yaml#
6 $schema: http://devicetree.org/meta-schemas/base.yaml#
8 title: Thermal zone
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
14 Thermal management is achieved in devicetree by describing the sensor hardware
15 and the software abstraction of cooling devices and thermal zones required to
16 take appropriate action to mitigate thermal overloads.
18 The following node types are used to completely describe a thermal management
[all …]
H A Dmediatek,lvts-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek SoC Low Voltage Thermal Sensor (LVTS)
10 - Balsam CHIHI <bchihi@baylibre.com>
13 LVTS is a thermal management architecture composed of three subsystems,
14 a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU),
15 a Converter - Low Voltage Thermal Sensor converter (LVTS), and
21 - mediatek,mt7988-lvts-ap
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
H A Darmada-ap806-dual.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu0: cpu@0 { label
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device tree sources for Exynos5433 thermal zone
8 #include <dt-bindings/thermal/thermal.h>
11 thermal-zones {
12 atlas0_thermal: atlas0-thermal {
13 thermal-sensors = <&tmu_atlas0>;
14 polling-delay-passive = <0>;
15 polling-delay = <0>;
17 atlas0_alert_0: atlas0-alert-0 {
22 atlas0_alert_1: atlas0-alert-1 {
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-thermal.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/thermal/thermal.h>
8 thermal_zones: thermal-zones {
9 main0_thermal: main0-thermal {
10 polling-delay-passive = <250>; /* milliSeconds */
11 polling-delay = <500>; /* milliSeconds */
12 thermal-sensors = <&wkup_vtm0 0>;
15 main0_alert: main0-alert {
21 main0_crit: main0-crit {
[all …]
H A Dk3-am652.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
17 cpu = <&cpu0>;
26 cpu0: cpu@0 { label
27 compatible = "arm,cortex-a53";
30 enable-method = "psci";
[all …]
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
17 cpu = <&cpu0>;
36 cpu0: cpu@0 { label
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
[all …]
H A Dk3-j721s2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
15 #include "k3-pinctrl.h"
21 interrupt-parent = <&gic500>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/allwinner/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu0: cpu@0 { label
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-a13.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/thermal/thermal.h>
50 thermal-zones {
51 cpu-thermal {
53 polling-delay-passive = <250>;
54 polling-delay = <1000>;
55 thermal-sensors = <&rtp>;
57 cooling-maps {
60 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
[all …]
H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-a1-ad402.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-a1.dtsi"
10 #include <dt-bindings/thermal/thermal.h>
21 stdout-path = "serial0:115200n8";
29 reserved-memory {
33 no-map;
39 compatible = "linaro,optee-tz";
44 battery_4v2: regulator-battery-4v2 {
45 compatible = "regulator-fixed";
[all …]
H A Dmeson-axg-jethome-jethub-j1xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "meson-axg.dtsi"
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/thermal/thermal.h>
24 stdout-path = "serial0:115200n8";
27 reserved-memory {
33 emmc_pwrseq: emmc-pwrseq {
34 compatible = "mmc-pwrseq-emmc";
35 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-cpu-thermal.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4/5 SoC CPU thermal
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
9 #include <dt-bindings/thermal/thermal.h>
12 polling-delay-passive = <250>; /* milliseconds */
13 polling-delay = <1000>; /* milliseconds */
19 thermal-sensors = <&bandgap 0>;
34 cpu_cooling_maps: cooling-maps {
37 cooling-device =
38 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
H A Domap443x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
12 cpu0: cpu@0 { label
13 /* OMAP443x variants OPP50-OPPNT */
14 operating-points = <
21 clock-latency = <300000>; /* From legacy driver */
24 #cooling-cells = <2>; /* min followed by max */
28 thermal-zones {
29 #include "omap4-cpu-thermal.dtsi"
37 compatible = "ti,omap4430-bandgap";
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih418.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/thermal/thermal.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
18 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
19 cpu-release-addr = <0x94100A4>;
[all …]
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
[all …]

123456