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/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
[all …]
H A Dopp.txt2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
8 uses CPU as a device.
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
26 cpu@0 {
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
[all …]
H A Dti-omap5-opp-supply.txt1 Texas Instruments OMAP compatible OPP supply description
9 Also, some supplies may have an associated vbb-supply which is an Adaptive Body
11 to the vdd-supply and clk when making an OPP transition. By supplying two
16 [1] Documentation/devicetree/bindings/opp/opp-v2.yaml
19 - vdd-supply: phandle to regulator controlling VDD supply
20 - vbb-supply: phandle to regulator controlling Body Bias supply
23 Required Properties for opp-supply node:
24 - compatible: Should be one of:
25 "ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB
26 "ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
9 source (usually MAINPLL) when the original CPU PLL is under
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
[all …]
H A Dnvidia,tegra20-cpufreq.txt5 - clocks: Must contain an entry for the CPU clock.
6 See ../clocks/clock-bindings.txt for details.
7 - operating-points-v2: See ../bindings/opp/opp-v2.yaml for details.
8 - #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
10 For each opp entry in 'operating-points-v2' table:
11 - opp-supported-hw: Two bitfields indicating:
13 1. CPU process ID mask
17 1. CPU process ID mask
18 2. CPU speedo ID mask
23 - opp-microvolt: CPU voltage triplet.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8996-oneplus-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
12 #include <dt-bindings/sound/qcom,q6afe.h>
13 #include <dt-bindings/sound/qcom,q6asm.h>
14 #include <dt-binding
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H A Dmsm8998-clamshell.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 vph_pwr: vph-pwr-regulator {
16 compatible = "regulator-fixed";
17 regulator-name = "vph_pwr";
18 regulator-always-on;
19 regulator-boot-on;
27 compatible = "qcom,wcn3990-bt";
29 vddio-supply = <&vreg_s4a_1p8>;
30 vddxo-supply = <&vreg_l7a_1p8>;
31 vddrf-supply = <&vreg_l17a_1p3>;
[all …]
H A Dsdm845-oneplus-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/input/linux-event-codes.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulato
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3368-lion.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
16 stdout-path = "serial0:115200n8";
19 ext_gmac: gmac-clk {
20 compatible = "fixed-clock";
21 clock-frequency = <125000000>;
22 clock-output-name
[all...]
H A Drk3588-rock-5b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
11 compatible = "radxa,rock-5b", "rockchip,rk3588";
20 stdout-path = "serial2:1500000n8";
23 analog-sound {
24 compatible = "audio-grap
[all...]
H A Dpx30-engicam-px30-core.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
13 compatible = "engicam,px30-core", "rockchip,px30";
21 cpu-supply = <&vdd_arm>;
25 cpu-supply = <&vdd_arm>;
29 cpu-supply = <&vdd_arm>;
33 cpu-supply = <&vdd_arm>;
37 cap-mmc-highspeed;
38 mmc-hs200-1_8v;
[all …]
H A Drk3328-rock64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
20 stdout-path = "serial2:1500000n8";
23 gmac_clkin: external-gmac-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-outpu
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-g12b-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 vddcpu_a: regulator-vddcpu-a {
15 compatible = "pwm-regulator";
17 regulator-name = "VDDCPU_A";
18 regulator-min-microvolt = <690000>;
19 regulator-max-microvolt = <1050000>;
21 pwm-supply = <&dc_in>;
24 pwm-dutycycle-range = <100 0>;
26 regulator-boot-on;
27 regulator-always-on;
[all …]
H A Dmeson-g12b-odroid.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/gpio/meson-g12a-gpio.h>
9 #include <dt-bindings/sound/meson-g12a-toacodec.h>
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
20 stdout-path = "serial0:115200n8";
28 emmc_pwrseq: emmc-pwrseq {
29 compatible = "mmc-pwrseq-emmc";
30 reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
33 fan: gpio-fan {
[all …]
H A Dmeson-g12b-w400.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b.dtsi"
11 #include "meson-g12b-s922x.dtsi"
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/gpio/meson-g12
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H A Dmeson-g12b-bananapi-cm4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12b-a311d.dtsi"
7 #include <dt-bindings/gpio/meson-g12a-gpio.h>
16 stdout-path = "serial0:115200n8";
19 emmc_pwrseq: emmc-pwrse
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu
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H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
14 stdout-path = "serial0:115200n8";
20 * missing a unit-address. However, the bootloader on these Chromebook
22 * Adding the unit-address causes the bootloader to create a /memory
34 /delete-node/ memory@80000000;
40 vdd-suppl
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/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsunxi-libretech-all-h3-it.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2019 Chen-Yu Tsai <wens@csie.org>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
14 stdout-path = "serial0:115200n8";
18 compatible = "hdmi-connector";
23 remote-endpoint = <&hdmi_out_con>;
29 compatible = "gpio-leds";
38 compatible = "regulator-fixed";
39 regulator-name = "vcc3v3";
[all …]
H A Dsunxi-bananapi-m2-plus-v1.2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
6 #include "sunxi-bananapi-m2-plus.dtsi"
11 * resistance on the CPU regulator's feedback pin.
13 reg_vdd_cpux: vdd-cpux {
14 compatible = "regulator-gpio";
15 regulator-name = "vdd-cpux";
16 regulator-type = "voltage";
17 regulator-boot-on;
18 regulator-always-on;
[all …]
H A Dsunxi-libretech-all-h3-cc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
16 stdout-path = "serial0:115200n8";
20 compatible = "hdmi-connector";
25 remote-endpoint = <&hdmi_out_con>;
31 compatible = "gpio-leds";
36 default-state = "on";
45 gpio-keys {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h6-tanix.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-h6.dtsi"
7 #include "sun50i-h6-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
17 stdout-path = "serial0:115200n8";
21 compatible = "hdmi-connector";
22 ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
27 remote-endpoint = <&hdmi_out_con>;
34 compatible = "i2c-gpio";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5420-arndale-octa.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "exynos5420-cpus.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/clock/samsung,s2mps11.h>
19 compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
32 stdout-path = "serial3:115200n8";
36 compatible = "samsung,secure-firmware";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3229-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/input/input.h>
10 compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
21 dc_12v: dc-12v-regulator {
22 compatible = "regulator-fixed";
23 regulator-name = "dc_12v";
24 regulator-always-on;
25 regulator-boot-on;
26 regulator-min-microvolt = <12000000>;
[all …]
H A Drk3229-xms6.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/input/input.h>
23 dc_12v: dc-12v-regulator {
24 compatible = "regulator-fixed";
25 regulator-name = "dc_12v";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-min-microvolt = <12000000>;
29 regulator-max-microvolt = <12000000>;
[all …]

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