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Searched +full:cpu +full:- +full:release +full:- +full:addr (Results 1 – 25 of 420) sorted by relevance

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/linux/arch/arm/boot/dts/intel/axm/
H A Daxm5516-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/boot/dts/axm5516-cpus.dtsi
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu-map {
16 cpu = <&CPU0>;
19 cpu = <&CPU1>;
22 cpu = <&CPU2>;
25 cpu = <&CPU3>;
30 cpu = <&CPU4>;
[all …]
/linux/drivers/soc/renesas/
H A Dr9a06g032-smp.c1 // SPDX-License-Identifier: GPL-2.0
8 * Derived from actions,s500-smp
17 * The second CPU is parked in ROM at boot time. It requires waking it after
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
35 r9a06g032_smp_boot_secondary(unsigned int cpu, in r9a06g032_smp_boot_secondary() argument
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
44 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
16 #include "multi-die-cpp.h"
18 #include "t600x-common.dtsi"
21 compatible = "apple,t6002", "apple,arm-platform";
23 #address-cells = <2>;
[all …]
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
25 cpu = <&cpu_e00>;
28 cpu = <&cpu_e01>;
34 cpu = <&cpu_p00>;
37 cpu = <&cpu_p01>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8-spin-table.dtsi8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
H A Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
38 #address-cells = <2>;
[all …]
/linux/arch/arm64/kernel/
H A Dsmp_spin_table.c1 // SPDX-License-Identifier: GPL-2.0-only
43 static int smp_spin_table_cpu_init(unsigned int cpu) in smp_spin_table_cpu_init() argument
48 dn = of_get_cpu_node(cpu, NULL); in smp_spin_table_cpu_init()
50 return -ENODEV; in smp_spin_table_cpu_init()
53 * Determine the address from which the CPU is polling. in smp_spin_table_cpu_init()
55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
56 &cpu_release_addr[cpu]); in smp_spin_table_cpu_init()
58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
59 cpu); in smp_spin_table_cpu_init()
66 static int smp_spin_table_cpu_prepare(unsigned int cpu) in smp_spin_table_cpu_prepare() argument
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_swvp.dts1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
49 enable-method = "spin-table";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih418-b2264.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2264", "st,stih418";
14 stdout-path = &sbc_serial0;
23 cpu@0 {
24 operating-points-v2 = <&cpu_opp_table>;
25 /* u-boot puts hpen in SBC dmem at 0xb8 offset */
26 cpu-release-addr = <0x94100b8>;
28 cpu@1 {
[all …]
H A Dstih418.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/thermal/thermal.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu2: cpu@2 {
15 device_type = "cpu";
16 compatible = "arm,cortex-a9";
[all …]
/linux/arch/arm/mach-sti/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-sti/platsmp.c
8 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
30 static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) in sti_boot_secondary() argument
35 * Secondary CPU is initialised and started by a U-BOOTROM firmware. in sti_boot_secondary()
36 * Secondary CPU is spinning and waiting for a write at cpu_strt_ptr. in sti_boot_secondary()
54 int cpu; in sti_smp_prepare_cpus() local
56 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in sti_smp_prepare_cpus()
67 for_each_possible_cpu(cpu) { in sti_smp_prepare_cpus()
69 np = of_get_cpu_node(cpu, NULL); in sti_smp_prepare_cpus()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992-lg-h815.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
16 /delete-node/ &cont_splash_mem;
19 /delete-node/ &dfps_data_mem;
24 chassis-type = "handset";
26 qcom,msm-id = <0xfb 0x0>;
27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
28 qcom,board-id = <0xb64 0x0>;
31 /delete-node/ psci;
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
[all …]
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dbooting.txt1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
45 這個術語來定義在將控制權交給 Linux 內核前 CPU 上執行的所有軟件。
58 -----------------
69 ---------------
81 -------------
91 -------------
111 - 自 v3.17 起，除非另有說明，所有域都是小端模式。
[all …]
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dbooting.txt12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
54 -----------------
65 ---------------
77 -------------
87 -------------
107 - 自 v3.17 起，除非另有说明，所有域都是小端模式。
109 - code0/code1 负责跳转到 stext.
[all …]
/linux/arch/powerpc/kernel/
H A Dmce.c1 // SPDX-License-Identifier: GPL-2.0-or-later
52 mce->error_type = mce_err->error_type; in mce_set_error_info()
53 switch (mce_err->error_type) { in mce_set_error_info()
55 mce->u.ue_error.ue_error_type = mce_err->u.ue_error_type; in mce_set_error_info()
58 mce->u.slb_error.slb_error_type = mce_err->u.slb_error_type; in mce_set_error_info()
61 mce->u.erat_error.erat_error_type = mce_err->u.erat_error_type; in mce_set_error_info()
64 mce->u.tlb_error.tlb_error_type = mce_err->u.tlb_error_type; in mce_set_error_info()
67 mce->u.user_error.user_error_type = mce_err->u.user_error_type; in mce_set_error_info()
70 mce->u.ra_error.ra_error_type = mce_err->u.ra_error_type; in mce_set_error_info()
73 mce->u.link_error.link_error_type = mce_err->u.link_error_type; in mce_set_error_info()
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb_common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
14 enable-method = "spin-table";
15 cpu-release-addr = /bits/ 64 <0>;
19 enable-method = "spin-table";
20 cpu-release-addr = /bits/ 64 <0>;
/linux/arch/sh/kernel/cpu/sh2/
H A Dsmp-j2.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
23 unsigned cpu = hard_smp_processor_id(); in j2_ipi_interrupt_handler() local
24 volatile unsigned *pmsg = &per_cpu(j2_ipi_messages, cpu); in j2_ipi_interrupt_handler()
48 np = of_find_compatible_node(NULL, NULL, "jcore,ipi-controller"); in j2_prepare_cpus()
57 np = of_find_compatible_node(NULL, NULL, "jcore,cpuid-mmio"); in j2_prepare_cpus()
79 static void j2_start_cpu(unsigned int cpu, unsigned long entry_point) in j2_start_cpu() argument
83 void __iomem *release, *initpc; in j2_start_cpu() local
85 if (!cpu) return; in j2_start_cpu()
87 np = of_get_cpu_node(cpu, NULL); in j2_start_cpu()
[all …]
/linux/arch/powerpc/platforms/44x/
H A Diss4xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright 2002-2005 MontaVista Software Inc.
12 * Copyright (c) 2003-2005 Zultys Technologies
54 for_each_node_with_property(np, "interrupt-controller") { in iss4xx_init_irq()
66 } else if (of_device_is_compatible(np, "chrp,open-pic")) { in iss4xx_init_irq()
68 * device-tree, just pass 0 to all arguments in iss4xx_init_irq()
80 static void smp_iss4xx_setup_cpu(int cpu) in smp_iss4xx_setup_cpu() argument
85 static int smp_iss4xx_kick_cpu(int cpu) in smp_iss4xx_kick_cpu() argument
87 struct device_node *cpunode = of_get_cpu_node(cpu, NULL); in smp_iss4xx_kick_cpu()
94 /* Assume spin table. We could test for the enable-method in in smp_iss4xx_kick_cpu()
[all …]
/linux/tools/memory-model/
H A Dlinux-kernel.cat1 // SPDX-License-Identifier: GPL-2.0+
9 * "Frightening small children and disconcerting grown-ups: Concurrency
14 "Linux-kernel memory consistency model"
27 (* Release Acquire *)
28 let acq-po = [Acquire] ; po ; [M]
29 let po-rel = [M] ; po ; [Release]
30 let po-unloc
[all...]
/linux/include/soc/fsl/
H A Dbman.h1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
34 /* wrapper for 48-bit buffers */
38 __be16 bpid; /* hi 8-bits reserved */
39 __be16 hi; /* High 16-bits of 48-bit address */
40 __be32 lo; /* Low 32-bits of 48-bit address */
51 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buf_addr()
56 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buffer_get64()
59 static inline void bm_buffer_set64(struct bm_buffer *buf, u64 addr) in bm_buffer_set64() argument
61 buf->hi = cpu_to_be16(upper_32_bits(addr)); in bm_buffer_set64()
62 buf->lo = cpu_to_be32(lower_32_bits(addr)); in bm_buffer_set64()
[all …]
/linux/include/linux/soc/marvell/octeontx2/
H A Dasm.h1 /* SPDX-License-Identifier: GPL-2.0-only
20 __asm__ volatile(".cpu generic+lse\n" \
27 * STEORL store to memory with release semantics.
31 #define cn10k_lmt_flush(val, addr) \ argument
33 __asm__ volatile(".cpu generic+lse\n" \
36 : [rs] "r"(addr)); \
43 asm volatile (".cpu generic+lse\n" in otx2_atomic64_fetch_add()
53 #define cn10k_lmt_flush(val, addr) ({ addr = val; }) argument
/linux/arch/arm/mach-axxia/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-axxia/platsmp.c
31 static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle) in axxia_boot_secondary() argument
37 syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon"); in axxia_boot_secondary()
39 return -ENOENT; in axxia_boot_secondary()
44 return -ENOMEM; in axxia_boot_secondary()
48 tmp &= ~(1 << cpu); in axxia_boot_secondary()
57 int cpu; in axxia_smp_prepare_cpus() local
63 for_each_possible_cpu(cpu) { in axxia_smp_prepare_cpus()
67 np = of_get_cpu_node(cpu, NULL); in axxia_smp_prepare_cpus()
[all …]

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