| /linux/drivers/cpufreq/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "CPU Frequency scaling"
5 bool "CPU Frequency scaling"
7 CPU Frequency scaling allows you to change the clock speed of
9 the lower the CPU clock speed, the less power the CPU consumes.
11 Note that this driver doesn't automatically change the CPU
16 <file:Documentation/admin-guide/pm/cpufreq.rst>.
31 bool "CPU frequency transition statistics"
33 Export CPU frequency statistics information through sysfs.
53 the CPU.
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| H A D | Kconfig.x86 | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # x86 CPU Frequency scaling drivers
14 This driver provides a P state for Intel core processors.
15 The driver implements an internal governor and will become
16 the scaling driver and governor for Sandy bridge processors.
18 When this driver is enabled it will become the preferred
19 scaling driver for Sandy bridge processors.
24 tristate "Processor Clocking Control interface driver"
27 This driver adds support for the PCC interface.
30 <file:Documentation/admin-guide/pm/cpufreq_drivers.rst>.
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| H A D | cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
9 * Oct 2005 - Ashok Raj <ashok.raj@intel.com>
10 * Added handling for CPU hotplug
11 * Feb 2006 - Jacob Shin <jacob.shin@amd.com>
12 * Fix handling for CPU hotplug -- affected CPUs
17 #include <linux/cpu.h>
37 /* Macros to iterate over CPU policies */
55 * The "cpufreq driver" - the arch- or hardware-dependent low
56 * level driver of CPUFreq support, and its spinlock. This lock
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| H A D | Kconfig.arm | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # ARM CPU Frequency scaling drivers
7 tristate "Allwinner nvmem based SUN50I CPUFreq driver"
12 This adds the nvmem based CPUFreq driver for Allwinner
15 To compile this driver as a module, choose M here: the
16 module will be called sun50i-cpufreq-nvmem.
25 This adds the CPUFreq driver for Airoha EN7581 SoCs.
33 This adds the CPUFreq driver for Apple Silicon machines
41 This adds the CPUFreq driver support for Marvell Armada 37xx SoCs.
45 tristate "Armada 8K CPUFreq driver"
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| /linux/drivers/cpuidle/ |
| H A D | Kconfig.arm | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # ARM CPU Idle drivers
6 bool "Generic ARM CPU idle Driver"
11 Select this to enable generic cpuidle driver for ARM.
12 It provides a generic idle driver whose idle states are configured
13 at run-time through DT nodes. The CPUidle suspend backend is
14 initialized by calling the CPU operations init idle hook
18 bool "PSCI CPU idle Driver"
23 Select this to enable PSCI firmware based CPUidle driver for ARM.
24 It provides an idle driver that is capable of detecting and
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| H A D | cpuidle-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU idle driver for Tegra CPUs
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
12 * Tegra20/124 driver unification by Dmitry Osipenko <digetx@gmail.com>
15 #define pr_fmt(fmt) "tegra-cpuidle: " fmt
53 unsigned long cpu, lcpu, csr; in tegra_cpuidle_report_cpus_state() local
56 cpu = cpu_logical_map(lcpu); in tegra_cpuidle_report_cpus_state()
57 csr = flowctrl_read_cpu_csr(cpu); in tegra_cpuidle_report_cpus_state()
59 pr_err("cpu%lu: online=%d flowctrl_csr=0x%08lx\n", in tegra_cpuidle_report_cpus_state()
60 cpu, cpu_online(lcpu), csr); in tegra_cpuidle_report_cpus_state()
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| H A D | cpuidle-psci.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PSCI CPU idle driver.
29 #include "cpuidle-psci.h"
58 u32 *states = data->psci_states; in __psci_enter_domain_idle_state()
59 struct device *pd_dev = data->dev; in __psci_enter_domain_idle_state()
65 return -1; in __psci_enter_domain_idle_state()
67 /* Do runtime PM to manage a hierarchical CPU toplogy. */ in __psci_enter_domain_idle_state()
77 ret = psci_cpu_suspend_enter(state) ? -1 : idx; in __psci_enter_domain_idle_state()
104 static int psci_idle_cpuhp_up(unsigned int cpu) in psci_idle_cpuhp_up() argument
114 static int psci_idle_cpuhp_down(unsigned int cpu) in psci_idle_cpuhp_down() argument
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| /linux/Documentation/admin-guide/pm/ |
| H A D | cpufreq.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 CPU Performance Scaling
15 The Concept of CPU Performance Scaling
20 Operating Performance Points or P-states (in ACPI terminology). As a rule,
22 can be retired by the CPU over a unit of time, but also the higher the clock
24 time (or the more power is drawn) by the CPU in the given P-state. Therefore
25 there is a natural tradeoff between the CPU capacity (the number of instructions
26 that can be executed over a unit of time) and the power drawn by the CPU.
29 as possible and then there is no reason to use any P-states different from the
30 highest one (i.e. the highest-performance frequency/voltage configuration
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| H A D | intel_pstate.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 ``intel_pstate`` CPU Performance Scaling Driver
17 :doc:`CPU performance scaling subsystem <cpufreq>` in the Linux kernel
18 (``CPUFreq``). It is a scaling driver for the Sandy Bridge and later
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
35 available frequencies due to the possible size of it, so the driver does not do
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
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| H A D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 ``intel_idle`` CPU Idle Time Management Driver
17 :doc:`CPU idle time management subsystem <cpuidle>` in the Linux kernel
18 (``CPUIdle``). It is the default CPU idle time management driver for the
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
27 logical CPU executing it is idle and so it may be possible to put some of the
28 processor's functional blocks into low-power states. That instruction takes two
29 arguments (passed in the ``EAX`` and ``ECX`` registers of the target CPU), the
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
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| H A D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 .. |cpufreq| replace:: :doc:`CPU Performance Scaling <cpufreq>`
8 CPU Idle Time Management
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
37 software as individual single-core processors. In other words, a CPU is an
43 program) at a time, it is a CPU. In that case, if the hardware is asked to
46 Second, if the processor is multi-core, each core in it is able to follow at
61 Finally, each core in a multi-core processor may be able to follow more than one
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| /linux/drivers/bus/ |
| H A D | mips_cdmm.c | 2 * Bus driver for MIPS Common Device Memory Map (CDMM).
4 * Copyright (C) 2014-2015 Imagination Technologies Ltd.
13 #include <linux/cpu.h>
53 for (; table->type; ++table) { in mips_cdmm_lookup()
54 ret = (dev->type == table->type); in mips_cdmm_lookup()
67 return mips_cdmm_lookup(cdrv->id_table, cdev) != NULL; in mips_cdmm_match()
75 retval = add_uevent_var(env, "CDMM_CPU=%u", cdev->cpu); in mips_cdmm_uevent()
79 retval = add_uevent_var(env, "CDMM_TYPE=0x%02x", cdev->type); in mips_cdmm_uevent()
83 retval = add_uevent_var(env, "CDMM_REV=%u", cdev->rev); in mips_cdmm_uevent()
87 retval = add_uevent_var(env, "MODALIAS=mipscdmm:t%02X", cdev->type); in mips_cdmm_uevent()
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| /linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
24 will dump related registers for every CPU; finally this is good for assistant
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| /linux/Documentation/admin-guide/thermal/ |
| H A D | intel_powerclamp.rst | 2 Intel Powerclamp Driver
6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
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| /linux/Documentation/driver-api/pm/ |
| H A D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 CPU Idle Time Management
13 CPU Idle Time Management Subsystem
21 belongs to. That can be done by making the idle logical CPU stop fetching
28 particular idle state. That is the role of the CPU idle time management
40 CPU Idle Time Governors
43 A CPU idle time (``CPUIdle``) governor is a bundle of policy code invoked when
81 (logical) CPU represented by the struct cpuidle_device object pointed
83 to by the ``drv`` argument represents the ``CPUIdle`` driver to be used
84 with that CPU (among other things, it should contain the list of
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| /linux/Documentation/mm/ |
| H A D | hmm.rst | 5 Provide infrastructure and helpers to integrate non-conventional memory (device
12 the CPU meaning that any valid pointer on the CPU is also a valid pointer
21 CPU page-table mirroring works and the purpose of HMM in this context. The
32 have historically managed their memory through dedicated driver specific APIs.
34 driver and regular application memory (private anonymous, shared memory, or
47 share) and memory allocated through the device driver API (this still ends up
52 complex data set needs to re-map all the pointer relations between each of its
78 coherency is often optional. Access to device memory from a CPU is even more
84 in the other direction: the CPU can only access a limited range of the device
95 two-way cache coherency between CPU and device and allow all atomic operations the
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| /linux/drivers/platform/x86/ |
| H A D | intel_ips.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2010 Intel Corporation
10 * Some Intel Ibex Peak based platforms support so-called "intelligent
11 * power sharing", which allows the CPU and GPU to cooperate to maximize
12 * performance within a given TDP (thermal design point). This driver
13 * performs the coordination between the CPU and GPU, monitors thermal and
16 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled
18 * performance by allocating more power or thermal budget to the CPU or GPU
22 * thermal headroom is available, the CPU and/or GPU power clamps may be
30 * written to those registers and write them to the CPU, but we currently
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| /linux/Documentation/cpu-freq/ |
| H A D | cpufreq-stats.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 3. Configuring cpufreq-stats
22 cpufreq-stats is a driver that provides CPU frequency statistics for each CPU.
25 in /sysfs (<sysfs root>/devices/system/cpu/cpuX/cpufreq/stats/) for each CPU.
28 This driver is designed to be independent of any particular cpufreq_driver
29 that may be running on your CPU. So, it will work with any cpufreq_driver.
37 - time_in_state
38 - total_trans
39 - trans_table
41 All the statistics will be from the time the stats driver has been inserted
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| H A D | cpu-drivers.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 How to Implement a new CPUFreq Processor Driver
10 - Dominik Brodowski <linux@brodo.de>
11 - Rafael J. Wysocki <rafael.j.wysocki@intel.com>
12 - Viresh Kumar <viresh.kumar@linaro.org>
18 1.2 Per-CPU Initialization
31 So, you just got a brand-new CPU / chipset with datasheets and want to
32 add cpufreq support for this CPU / chipset? Great. Here are some hints
37 ------------------
40 function check whether this kernel runs on the right CPU and the right
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| /linux/Documentation/networking/device_drivers/ethernet/freescale/ |
| H A D | dpaa.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 The QorIQ DPAA Ethernet Driver
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
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| /linux/drivers/tty/ |
| H A D | mips_ejtag_fdc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TTY driver for MIPS EJTAG Fast Debug Channels.
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
89 * @driver: TTY driver.
106 struct mips_ejtag_fdc_tty *driver; member
117 * struct mips_ejtag_fdc_tty - Drive
143 struct tty_driver *driver; global() member
144 unsigned int cpu; global() member
309 unsigned int i, buf_len, cpu; mips_ejtag_fdc_console_write() local
761 mips_ejtag_fdc_tty_install(struct tty_driver * driver,struct tty_struct * tty) mips_ejtag_fdc_tty_install() argument
890 struct tty_driver *driver; mips_ejtag_fdc_tty_probe() local
1162 unsigned int cpu; kgdbfdc_setup() local
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| /linux/drivers/crypto/caam/ |
| H A D | qi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright 2013-2016 Freescale Semiconductor, Inc.
6 * Copyright 2016-2017, 2020 NXP
19 /* Length of a single buffer in the QI driver memory cache */
25 * This is the request structure the driver application should fill while
26 * submitting a job to driver.
31 * caam_qi_cbk - application's callback function invoked by the driver when the
34 * @status: completion status of request (0 - success, non-zero - error code)
45 * caam_drv_ctx - CAAM/QI backend driver context
47 * The jobs are processed by the driver against a driver context.
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| /linux/Documentation/driver-api/ |
| H A D | io_ordering.rst | 2 Ordering I/O writes to memory-mapped addresses
5 On some platforms, so-called memory-mapped I/O is weakly ordered. On such
6 platforms, driver writers are responsible for ensuring that I/O writes to
7 memory-mapped addresses on their device arrive in the order intended. This is
10 driver would usually use this technique immediately prior to the exit of a
15 A more concrete example from a hypothetical device driver::
18 CPU A: spin_lock_irqsave(&dev_lock, flags)
19 CPU A: val = readl(my_status);
20 CPU A: ...
21 CPU A: writel(newval, ring_ptr);
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| /linux/Documentation/networking/dsa/ |
| H A D | dsa.rst | 22 An Ethernet switch typically comprises multiple front-panel ports and one
23 or more CPU or management ports. The DSA subsystem currently relies on the
27 gateways, or even top-of-rack switches. This host Ethernet controller will
28 be later referred to as "conduit" and "cpu" in DSA terminology and code.
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
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| /linux/Documentation/hwmon/ |
| H A D | asus_wmi_sensors.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver asus_wmi_sensors
7 * PRIME X399-A,
8 * PRIME X470-PRO,
11 * ROG CROSSHAIR VI HERO (WI-FI AC),
13 * ROG CROSSHAIR VII HERO (WI-FI),
14 * ROG STRIX B450-E GAMING,
15 * ROG STRIX B450-F GAMING,
16 * ROG STRIX B450-I GAMING,
17 * ROG STRIX X399-E GAMING,
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