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/linux/arch/mips/kernel/
H A Dcevt-bcm1480.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
34 void __iomem *cfg, *init; in sibyte_set_periodic() local
36 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
37 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INI in sibyte_set_periodic()
47 unsigned int cpu = smp_processor_id(); sibyte_shutdown() local
48 void __iomem *cfg; sibyte_shutdown() local
59 unsigned int cpu = smp_processor_id(); sibyte_next_event() local
60 void __iomem *cfg, *init; sibyte_next_event() local
74 unsigned int cpu = smp_processor_id(); sibyte_counter_handler() local
76 void __iomem *cfg; sibyte_counter_handler() local
98 unsigned int cpu = smp_processor_id(); sb1480_clockevent_init() local
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H A Dcevt-sb1250.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 void __iomem *cfg; in sibyte_shutdown() local
33 cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); in sibyte_shutdown()
36 __raw_writeq(0, cfg); in sibyte_shutdown()
43 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
44 void __iomem *cfg, *init; in sibyte_set_periodic() local
46 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
47 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
49 __raw_writeq(0, cfg); in sibyte_set_periodic()
50 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
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H A Dsmp-bmips.c20 #include <linux/cpu.h>
40 #include <asm/cpu-features.h>
53 static void bmips_set_reset_vec(int cpu, u32 val);
59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
63 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
64 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
72 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) argument
73 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
74 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
75 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) argument
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H A Dcpu-r3k-probe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1994 - 2006 Ralf Baechle
18 #include <asm/cpu.h>
19 #include <asm/cpu-features.h>
20 #include <asm/cpu-type.h>
26 #include "fpu-probe.h"
38 * Probe whether cpu has config register by trying to play with
46 unsigned long cfg = read_c0_conf(); in cpu_has_confreg() local
49 write_c0_conf(cfg ^ R30XX_CONF_AC); in cpu_has_confreg()
51 write_c0_conf(cfg); in cpu_has_confreg()
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/linux/arch/arm/mach-omap2/
H A Domap-smp.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
52 static struct omap_smp_config cfg; variable
71 return cfg.scu_base; in omap4_get_scu_base()
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
100 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", in omap5_erratum_workaround_801819()
139 pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n", in omap5_secondary_harden_predictor()
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/linux/arch/x86/kernel/
H A Dhpet.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/cpu.h>
29 unsigned int cpu; member
134 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
144 u32 i, id, period, cfg, status, channels, l, h; in _hpet_print_config() local
152 cfg = hpet_readl(HPET_CFG); in _hpet_print_config()
154 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); in _hpet_print_config()
211 hd.hd_irq[i] = hc->irq; in hpet_reserve_platform_timers()
213 switch (hc->mode) { in hpet_reserve_platform_timers()
216 hc->mode = HPET_MODE_DEVICE; in hpet_reserve_platform_timers()
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/linux/arch/mips/loongson64/
H A Dhpet.c1 // SPDX-License-Identifier: GPL-2.0
35 unsigned int cfg = smbus_read(offset); in smbus_enable() local
37 cfg |= bit; in smbus_enable()
38 smbus_write(offset, cfg); in smbus_enable()
53 unsigned int cfg = hpet_read(HPET_CFG); in hpet_start_counter() local
55 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
56 hpet_write(HPET_CFG, cfg); in hpet_start_counter()
61 unsigned int cfg = hpet_read(HPET_CFG); in hpet_stop_counter() local
63 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
64 hpet_write(HPET_CFG, cfg); in hpet_stop_counter()
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/linux/drivers/tty/
H A Dmips_ejtag_fdc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
120 * @cpu: CPU number for this FDC.
123 * @ports: Per-channel data.
144 unsigned int cpu; member
309 unsigned int i, buf_len, cpu; mips_ejtag_fdc_console_write() local
488 u32 cfg; mips_ejtag_fdc_put() local
561 unsigned int stat, channel, data, cfg, i, flipped; mips_ejtag_fdc_handle() local
891 unsigned int cfg, tx_fifo; mips_ejtag_fdc_tty_probe() local
1051 unsigned int cfg; mips_ejtag_fdc_tty_cpu_down() local
1074 unsigned int cfg; mips_ejtag_fdc_tty_cpu_up() local
1162 unsigned int cpu; kgdbfdc_setup() local
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/linux/arch/arm/mach-s3c/
H A Dinit.c1 // SPDX-License-Identifier: GPL-2.0
7 // S3C series CPU initialisation
26 #include "cpu.h"
29 static struct cpu_table *cpu; variable
35 for (; count != 0; count--, tab++) { in s3c_lookup_cpu()
36 if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) in s3c_lookup_cpu()
46 cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); in s3c_init_cpu()
48 if (cpu == NULL) { in s3c_init_cpu()
49 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); in s3c_init_cpu()
50 panic("Unknown S3C24XX CPU"); in s3c_init_cpu()
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H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2004-2005 Simtec Electronics
9 * Header file for Samsung CPU support
12 /* todo - fix when rmk changes iodescs to use `void __iomem *` */
57 /* per-cpu initialisation function table. */
63 void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
74 extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
77 struct s3c2410_uartcfg *cfg, int no);
/linux/tools/testing/selftests/bpf/map_tests/
H A Dtask_storage_map.c1 // SPDX-License-Identifier: GPL-2.0
34 while (!ctx->start) in lookup_fn()
37 while (!ctx->stop && i++ < ctx->loop) in lookup_fn()
38 bpf_map_lookup_elem(ctx->map_fd, &ctx->pid_fd, &value); in lookup_fn()
46 ctx->stop = true; in abort_lookup()
47 ctx->start = true; in abort_lookup()
55 unsigned int i, nr = 256, loop = 8192, cpu = 0; in test_task_storage_map_stress_lookup() local
60 const char *cfg; in test_task_storage_map_stress_lookup() local
63 cfg = getenv("TASK_STORAGE_MAP_NR_THREAD"); in test_task_storage_map_stress_lookup()
64 if (cfg) { in test_task_storage_map_stress_lookup()
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/linux/drivers/irqchip/
H A Dirq-ls-scfg-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale SCFG MSI(-X) support
53 struct ls_scfg_msi_cfg *cfg; member
77 if (p && strncmp(p, "no-affinity", 11) == 0) in early_parse_ls_scfg_msi()
90 msg->address_hi = upper_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
91 msg->address_lo = lower_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
92 msg->data = data->hwirq; in ls_scfg_msi_compose_msg()
98 msg->data |= cpumask_first(mask); in ls_scfg_msi_compose_msg()
108 u32 cpu; in ls_scfg_msi_set_affinity() local
111 return -EINVAL; in ls_scfg_msi_set_affinity()
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/linux/arch/arm/mach-imx/
H A Dmmdc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
76 { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
77 { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
86 PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
87 PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
88 PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
89 PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
90 PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
91 PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
92 PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
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/linux/drivers/clk/samsung/
H A Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * This file contains the utility function to register CPU clock for Samsung
10 * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
11 * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxiliary clocks of the CPU
22 * registers to achieve a fast coordinated rate change for all the CPU domain
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/linux/include/linux/perf/
H A Darm_pmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters.
21 * The Armv8.9/9.4 CPU PMU supports up to 33 event counters.
44 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
47 [0 ... C(MAX) - 1] = { \
48 [0 ... C(OP_MAX) - 1] = { \
49 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
68 * already have to allocate this struct per cpu.
104 bool secure_access; /* 32-bit ARM only */
113 /* the attr_groups array must be NULL-terminated */
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/linux/drivers/perf/
H A Dcxl_pmu.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/io-64-nonatomic-lo-hi.h>
66 /* CXL rev 3.0 Table 13-5 Events under CXL Vendor ID */
120 * - Fixed function counters refer to an Event Capabilities register.
127 void __iomem *base = info->base; in cxl_pmu_parse_caps()
137 return -ENODEV; in cxl_pmu_parse_caps()
140 info->num_counters = FIELD_GET(CXL_PMU_CAP_NUM_COUNTERS_MSK, val) + 1; in cxl_pmu_parse_caps()
141 info->counter_width = FIELD_GET(CXL_PMU_CAP_COUNTER_WIDTH_MSK, val); in cxl_pmu_parse_caps()
142 info->num_event_capabilities = FIELD_GET(CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1; in cxl_pmu_parse_caps()
144 info->filter_hdm = FIELD_GET(CXL_PMU_CAP_FILTERS_SUP_MSK, val) & CXL_PMU_FILTER_HDM; in cxl_pmu_parse_caps()
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/linux/arch/x86/pci/
H A Dmmconfig_32.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
29 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in get_base_addr() local
31 if (cfg) in get_base_addr()
32 return cfg->address; in get_base_addr()
42 int cpu = smp_processor_id(); in pci_exp_set_dev_base() local
44 cpu != mmcfg_last_accessed_cpu) { in pci_exp_set_dev_base()
46 mmcfg_last_accessed_cpu = cpu; in pci_exp_set_dev_base()
58 err: *value = -1; in pci_mmcfg_read()
59 return -EINVAL; in pci_mmcfg_read()
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/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-fw-com.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
7 #include <linux/dma-mapping.h>
14 #include "ipu6-bus.h"
15 #include "ipu6-dma.h"
16 #include "ipu6-fw-com.h"
23 * system RAM and are mapped to ISP MMU so that both CPU and ISP can
25 * can poll those with very low latency and cost. CPU access to indexes is
27 * interrupt triggered message handling. CPU doesn't need to poll indexes.
32 /* Shared structure between driver and FW - do not modify */
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/linux/drivers/spi/
H A Dspi-pxa2xx-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
21 #include "spi-pxa2xx.h"
28 struct spi_message *msg = drv_data->controller->cur_msg; in pxa2xx_spi_dma_transfer_complete()
31 * It is possible that one CPU is handling ROR interrupt and other in pxa2xx_spi_dma_transfer_complete()
36 if (atomic_dec_and_test(&drv_data->dma_running)) { in pxa2xx_spi_dma_transfer_complete()
38 * If the other CPU is still handling the ROR interrupt we in pxa2xx_spi_dma_transfer_complete()
39 * might not know about the error yet. So we re-check the in pxa2xx_spi_dma_transfer_complete()
43 error = read_SSSR_bits(drv_data, drv_data->mask_sr) & SSSR_ROR; in pxa2xx_spi_dma_transfer_complete()
46 clear_SSCR1_bits(drv_data, drv_data->dma_cr1); in pxa2xx_spi_dma_transfer_complete()
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/linux/arch/mips/mm/
H A Dinit.c6 * Copyright (C) 1994 - 2000 Ralf Baechle
38 #include <asm/cpu.h>
81 zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK; in setup_zero_pages()
97 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); in __kmap_pgprot()
99 vaddr = __fix_to_virt(FIX_CMAP_END - idx); in __kmap_pgprot()
156 wired = num_wired_entries() - 1; in kunmap_coherent()
192 /* Make sure this page is cleared on other CPU's too before using it */ in copy_user_highpage()
212 if (vma->vm_flags & VM_EXEC) in copy_to_user_page()
278 struct maar_config cfg[16]; member
286 struct maar_config *cfg = &wi->cfg[wi->num_cfg]; in maar_res_walk() local
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/linux/arch/sparc/kernel/
H A Dleon_smp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* leon_smp.c: Sparc-Leon SMP support.
27 #include <linux/cpu.h>
81 * go-ahead by setting the smp_commenced_mask and will wait without in leon_cpu_pre_online()
87 local_ops->cache_all(); in leon_cpu_pre_online()
88 local_ops->tlb_all(); in leon_cpu_pre_online()
96 current->active_mm = &init_mm; in leon_cpu_pre_online()
110 unsigned long cfg = sparc_leon3_get_dcachecfg(); in leon_configure_cache_smp() local
113 if (ASI_LEON3_SYSCTRL_CFG_SSIZE(cfg) > 4) { in leon_configure_cache_smp()
114 …printk(KERN_INFO "Note: SMP with snooping only works on 4k cache, found %dk(0x%x) on cpu %d, disab… in leon_configure_cache_smp()
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/linux/drivers/macintosh/
H A Dwindfarm_lm75_sensor.c1 // SPDX-License-Identifier: GPL-2.0-only
48 if (lm->i2c == NULL) in wf_lm75_get()
49 return -ENODEV; in wf_lm75_get()
52 if (!lm->inited) { in wf_lm75_get()
53 u8 cfg_new, cfg = (u8)i2c_smbus_read_byte_data(lm->i2c, 1); in wf_lm75_get() local
55 DBG("wf_lm75: Initializing %s, cfg was: %02x\n", in wf_lm75_get()
56 sr->name, cfg); in wf_lm75_get()
61 cfg_new = cfg & ~0x01; in wf_lm75_get()
62 i2c_smbus_write_byte_data(lm->i2c, 1, cfg_new); in wf_lm75_get()
63 lm->inited = 1; in wf_lm75_get()
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/linux/drivers/clk/
H A Dclk-k210.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #define pr_fmt(fmt) "k210-clk: " fmt
15 #include <linux/clk-provider.h>
18 #include <soc/canaan/k210-sysctl.h>
20 #include <dt-bindings/clock/k210-clk.h>
66 .name = "cpu",
301 * The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0
322 * struct k210_sysclk - sysclk driver data
356 pll->id = pllid; in k210_init_pll()
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/linux/arch/x86/kernel/apic/
H A Dx2apic_phys.c1 // SPDX-License-Identifier: GPL-2.0
16 if (apic->x2apic_set_max_apicid) in x2apic_set_max_apicid()
17 apic->max_apic_id = apicid; in x2apic_set_max_apicid()
44 static void x2apic_send_IPI(int cpu, int vector) in x2apic_send_IPI() argument
46 u32 dest = per_cpu(x86_cpu_to_apicid, cpu); in x2apic_send_IPI()
88 unsigned long cfg = __prepare_ICR(which, vector, 0); in __x2apic_send_IPI_shorthand() local
92 native_x2apic_icr_write(cfg, 0); in __x2apic_send_IPI_shorthand()
112 unsigned long cfg = __prepare_ICR(0, vector, dest); in __x2apic_send_IPI_dest() local
113 native_x2apic_icr_write(cfg, apicid); in __x2apic_send_IPI_dest()
/linux/tools/power/pm-graph/
H A DREADME8 pm-graph: suspend/resume/boot timing analysis tools
11 …Home Page: https://www.intel.com/content/www/us/en/developer/topic-technology/open/pm-graph/overvi…
13 Report bugs/issues at bugzilla.kernel.org Tools/pm-graph
14 - https://bugzilla.kernel.org/buglist.cgi?component=pm-graph&product=Tools
17 - Getting Started:
20 - Feature Summary:
21 https://www.intel.com/content/www/us/en/developer/topic-technology/open/pm-graph/features.html
23 - upstream version in git:
24 git clone https://github.com/intel/pm-graph/
27 - Overview
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