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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g011.dtsi9 #include <dt-bindings/clock/r9a09g011-cpg.h>
42 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
[all …]
H A Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
83 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
94 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
153 clocks = <&cpg CPG_MOD 402>;
155 resets = <&cpg 402>;
169 clocks = <&cpg CPG_MOD 912>;
171 resets = <&cpg 912>;
184 clocks = <&cpg CPG_MOD 911>;
186 resets = <&cpg 911>;
199 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr9a07g043u.dtsi28 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
66 clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
67 <&cpg CPG_MOD R9A07G043_CRU_PCLK>,
68 <&cpg CPG_MOD R9A07G043_CRU_ACLK>;
74 resets = <&cpg R9A07G043_CRU_PRESETN>,
75 <&cpg R9A07G043_CRU_ARESETN>;
77 power-domains = <&cpg>;
101 clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
102 <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
103 <&cpg CPG_MOD R9A07G043_CRU_PCLK>;
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
72 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
83 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
134 clocks = <&cpg CPG_MOD 402>;
136 resets = <&cpg 402>;
150 clocks = <&cpg CPG_MOD 912>;
152 resets = <&cpg 912>;
165 clocks = <&cpg CPG_MOD 911>;
167 resets = <&cpg 911>;
180 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
66 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
124 clocks = <&cpg CPG_MOD 402>;
126 resets = <&cpg 402>;
140 clocks = <&cpg CPG_MOD 912>;
142 resets = <&cpg 912>;
155 clocks = <&cpg CPG_MOD 911>;
157 resets = <&cpg 911>;
170 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7744.dtsi10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
46 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
99 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
167 clocks = <&cpg CPG_MOD 402>;
169 resets = <&cpg 402>;
183 clocks = <&cpg CPG_MOD 912>;
185 resets = <&cpg 912>;
198 clocks = <&cpg CPG_MOD 911>;
200 resets = <&cpg 911>;
213 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
85 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
139 clocks = <&cpg CPG_MOD 912>;
141 resets = <&cpg 912>;
154 clocks = <&cpg CPG_MOD 911>;
156 resets = <&cpg 911>;
169 clocks = <&cpg CPG_MOD 910>;
171 resets = <&cpg 910>;
184 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
79 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
101 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
123 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
145 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
167 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
179 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
191 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
203 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
280 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a7742.dtsi8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
57 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
101 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
123 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
145 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
155 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
165 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
175 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
248 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
91 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
152 clocks = <&cpg CPG_MOD 402>;
154 resets = <&cpg 402>;
168 clocks = <&cpg CPG_MOD 912>;
170 resets = <&cpg 912>;
183 clocks = <&cpg CPG_MOD 911>;
185 resets = <&cpg 911>;
198 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr7s9210.dtsi10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
81 clocks = <&cpg CPG_MOD 47>;
83 power-domains = <&cpg>;
98 clocks = <&cpg CPG_MOD 46>;
100 power-domains = <&cpg>;
115 clocks = <&cpg CPG_MOD 45>;
117 power-domains = <&cpg>;
132 clocks = <&cpg CPG_MOD 44>;
134 power-domains = <&cpg>;
149 clocks = <&cpg CPG_MOD 43>;
[all …]
/linux/drivers/clk/renesas/
H A Dclk-r8a7740.c3 * r8a7740 Core CPG Clocks
61 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, in r8a7740_cpg_register_clock() argument
139 table, &cpg->lock); in r8a7740_cpg_register_clock()
145 struct r8a7740_cpg *cpg; in r8a7740_cpg_clocks_init() local
160 cpg = kzalloc_obj(*cpg); in r8a7740_cpg_clocks_init()
162 if (cpg == NULL || clks == NULL) { in r8a7740_cpg_clocks_init()
169 spin_lock_init(&cpg->lock); in r8a7740_cpg_clocks_init()
171 cpg->data.clks = clks; in r8a7740_cpg_clocks_init()
172 cpg->data.clk_num = num_clks; in r8a7740_cpg_clocks_init()
185 clk = r8a7740_cpg_register_clock(np, cpg, base, name); in r8a7740_cpg_clocks_init()
[all …]
H A Dclk-sh73a0.c3 * sh73a0 Core CPG Clocks
72 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
155 table, &cpg->lock); in sh73a0_cpg_register_clock()
161 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
173 cpg = kzalloc_obj(*cpg); in sh73a0_cpg_clocks_init()
175 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
182 spin_lock_init(&cpg->lock); in sh73a0_cpg_clocks_init()
184 cpg->data.clks = clks; in sh73a0_cpg_clocks_init()
185 cpg->data.clk_num = num_clks; in sh73a0_cpg_clocks_init()
203 clk = sh73a0_cpg_register_clock(np, cpg, base, name); in sh73a0_cpg_clocks_init()
[all …]
H A Dclk-r8a73a4.c3 * r8a73a4 Core CPG Clocks
60 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, in r8a73a4_cpg_register_clock() argument
183 table, &cpg->lock); in r8a73a4_cpg_register_clock()
189 struct r8a73a4_cpg *cpg; in r8a73a4_cpg_clocks_init() local
201 cpg = kzalloc_obj(*cpg); in r8a73a4_cpg_clocks_init()
203 if (cpg == NULL || clks == NULL) { in r8a73a4_cpg_clocks_init()
210 spin_lock_init(&cpg->lock); in r8a73a4_cpg_clocks_init()
212 cpg->data.clks = clks; in r8a73a4_cpg_clocks_init()
213 cpg->data.clk_num = num_clks; in r8a73a4_cpg_clocks_init()
226 clk = r8a73a4_cpg_register_clock(np, cpg, base, name); in r8a73a4_cpg_clocks_init()
[all …]
H A Drenesas-cpg-mssr.c31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
179 * @dev: CPG/MSSR device
180 * @reg_layout: CPG/MSSR register layout
181 * @np: Device node in DT for this CPG/MSSR module
229 * @priv: CPG/MSSR private data
404 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); in cpg_mssr_clk_src_twocell_get()
612 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); in cpg_mssr_attach_dev()
892 .compatible = "renesas,r7s9210-cpg-mssr",
898 .compatible = "renesas,r8a7742-cpg-mssr",
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rzv2h-cpg.yaml4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
7 title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
13 On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
21 - renesas,r9a09g047-cpg # RZ/G3E
22 - renesas,r9a09g056-cpg # RZ/V2N
23 - renesas,r9a09g057-cpg # RZ/V2H
42 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
44 <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
77 compatible = "renesas,r9a09g057-cpg";
H A Drenesas,cpg-div6-clock.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
7 title: Renesas CPG DIV6 Clock
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14 Generator (CPG). Their clock input is divided by a configurable factor from 1
24 - const: renesas,cpg-div6-clock
56 compatible = "renesas,r8a73a4-cpg-clocks";
67 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
H A Drenesas,cpg-mstp-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
30 - const: renesas,cpg-mstp-clocks
68 "renesas,cpg-mstp-clocks";
/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,lvds.yaml142 #include <dt-bindings/clock/renesas-cpg-mssr.h>
148 clocks = <&cpg CPG_MOD 727>;
150 resets = <&cpg 727>;
172 #include <dt-bindings/clock/renesas-cpg-mssr.h>
178 clocks = <&cpg CPG_MOD 727>,
183 resets = <&cpg 727>;
209 clocks = <&cpg CPG_MOD 727>,
214 resets = <&cpg 726>;
/linux/Documentation/devicetree/bindings/spi/
H A Drenesas,rzv2m-csi.yaml67 #include <dt-bindings/clock/r9a09g011-cpg.h>
72 clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
73 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
75 resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
76 power-domains = <&cpg>;
/linux/Documentation/devicetree/bindings/thermal/
H A Drcar-gen3-thermal.yaml104 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
116 clocks = <&cpg CPG_MOD 522>;
118 resets = <&cpg 522>;
138 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
149 clocks = <&cpg CPG_MOD 919>;
151 resets = <&cpg 919>;
/linux/Documentation/devicetree/bindings/media/
H A Drenesas,drif.yaml168 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
181 clocks = <&cpg CPG_MOD 515>;
187 resets = <&cpg 515>;
203 clocks = <&cpg CPG_MOD 514>;
209 resets = <&cpg 514>;
225 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
238 clocks = <&cpg CPG_MOD 513>;
243 resets = <&cpg 513>;
252 clocks = <&cpg CPG_MOD 512>;
257 resets = <&cpg 512>;

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