Home
last modified time | relevance | path

Searched full:cpg (Results 1 – 25 of 243) sorted by relevance

12345678910

/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
[all …]
H A Dr9a07g054.dtsi9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
356 clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
357 resets = <&cpg R9A07G054_GPT_RST_C>;
358 power-domains = <&cpg>;
370 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
[all …]
H A Dr9a07g044.dtsi9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
356 clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
357 resets = <&cpg R9A07G044_GPT_RST_C>;
358 power-domains = <&cpg>;
370 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
[all …]
H A Dr9a09g011.dtsi9 #include <dt-bindings/clock/r9a09g011-cpg.h>
41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
[all …]
H A Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
101 clocks = <&cpg CPG_MOD 402>;
103 resets = <&cpg 402>;
117 clocks = <&cpg CPG_MOD 912>;
119 resets = <&cpg 912>;
132 clocks = <&cpg CPG_MOD 911>;
134 resets = <&cpg 911>;
147 clocks = <&cpg CPG_MOD 910>;
149 resets = <&cpg 910>;
162 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr9a07g043u.dtsi26 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
66 clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
67 <&cpg CPG_MOD R9A07G043_CRU_PCLK>,
68 <&cpg CPG_MOD R9A07G043_CRU_ACLK>;
74 resets = <&cpg R9A07G043_CRU_PRESETN>,
75 <&cpg R9A07G043_CRU_ARESETN>;
77 power-domains = <&cpg>;
101 clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
102 <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
103 <&cpg CPG_MOD R9A07G043_CRU_PCLK>;
[all …]
H A Dr8a779f0.dtsi8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
121 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
145 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
157 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
169 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
181 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
193 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
205 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
312 clocks = <&cpg CPG_MOD 907>;
[all …]
H A Dulcb.dtsi377 clocks = <&cpg CPG_MOD 1005>,
378 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
379 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
380 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
381 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
382 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
383 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
384 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
385 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
386 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
H A Debisu.dtsi368 clocks = <&cpg CPG_MOD 724>,
369 <&cpg CPG_MOD 723>,
546 clocks = <&cpg CPG_MOD 727>,
568 clocks = <&cpg CPG_MOD 727>,
719 clocks = <&cpg CPG_MOD 1005>,
720 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
721 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
722 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
723 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
724 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
[all …]
H A Dsalvator-common.dtsi808 clocks = <&cpg CPG_MOD 1005>,
809 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
810 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
811 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
812 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
813 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
814 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
815 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
816 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
817 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
71 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
134 clocks = <&cpg CPG_MOD 402>;
136 resets = <&cpg 402>;
150 clocks = <&cpg CPG_MOD 912>;
152 resets = <&cpg 912>;
165 clocks = <&cpg CPG_MOD 911>;
167 resets = <&cpg 911>;
180 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
124 clocks = <&cpg CPG_MOD 402>;
126 resets = <&cpg 402>;
140 clocks = <&cpg CPG_MOD 912>;
142 resets = <&cpg 912>;
155 clocks = <&cpg CPG_MOD 911>;
157 resets = <&cpg 911>;
170 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
77 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
167 clocks = <&cpg CPG_MOD 402>;
169 resets = <&cpg 402>;
183 clocks = <&cpg CPG_MOD 912>;
185 resets = <&cpg 912>;
198 clocks = <&cpg CPG_MOD 911>;
200 resets = <&cpg 911>;
213 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
122 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
144 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
166 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
178 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
190 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
202 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
280 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
152 clocks = <&cpg CPG_MOD 402>;
154 resets = <&cpg 402>;
168 clocks = <&cpg CPG_MOD 912>;
170 resets = <&cpg 912>;
183 clocks = <&cpg CPG_MOD 911>;
185 resets = <&cpg 911>;
198 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr7s9210.dtsi10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
82 clocks = <&cpg CPG_MOD 47>;
84 power-domains = <&cpg>;
99 clocks = <&cpg CPG_MOD 46>;
101 power-domains = <&cpg>;
116 clocks = <&cpg CPG_MOD 45>;
118 power-domains = <&cpg>;
133 clocks = <&cpg CPG_MOD 44>;
135 power-domains = <&cpg>;
150 clocks = <&cpg CPG_MOD 43>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
[all …]
H A Drenesas,rzv2h-cpg.yaml4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
7 title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
13 On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
21 - renesas,r9a09g047-cpg # RZ/G3E
22 - renesas,r9a09g056-cpg # RZ/V2N
23 - renesas,r9a09g057-cpg # RZ/V2H
42 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
44 <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
77 compatible = "renesas,r9a09g057-cpg";
H A Drenesas,cpg-div6-clock.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
7 title: Renesas CPG DIV6 Clock
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14 Generator (CPG). Their clock input is divided by a configurable factor from 1
24 - const: renesas,cpg-div6-clock
56 compatible = "renesas,r8a73a4-cpg-clocks";
67 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml135 #include <dt-bindings/clock/r9a07g044-cpg.h>
150 clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
151 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
152 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
153 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
154 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
155 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
157 resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
158 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
159 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
[all …]
/linux/arch/arm/mach-shmobile/
H A Dsetup-rcar-gen2.c22 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
23 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
24 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
25 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
26 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
27 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
34 struct device_node *cpg, *extal; in get_extal_freq() local
38 cpg = of_find_matching_node_and_match(NULL, cpg_matches, &match); in get_extal_freq()
39 if (!cpg) in get_extal_freq()
43 idx = of_property_match_string(cpg, "clock-names", match->data); in get_extal_freq()
[all …]
/linux/drivers/clk/renesas/
H A Dclk-r8a7740.c3 * r8a7740 Core CPG Clocks
59 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, in r8a7740_cpg_register_clock() argument
137 table, &cpg->lock); in r8a7740_cpg_register_clock()
143 struct r8a7740_cpg *cpg; in r8a7740_cpg_clocks_init() local
158 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a7740_cpg_clocks_init()
160 if (cpg == NULL || clks == NULL) { in r8a7740_cpg_clocks_init()
167 spin_lock_init(&cpg->lock); in r8a7740_cpg_clocks_init()
169 cpg->data.clks = clks; in r8a7740_cpg_clocks_init()
170 cpg->data.clk_num = num_clks; in r8a7740_cpg_clocks_init()
183 clk = r8a7740_cpg_register_clock(np, cpg, base, name); in r8a7740_cpg_clocks_init()
[all …]
H A Dclk-sh73a0.c3 * sh73a0 Core CPG Clocks
72 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
155 table, &cpg->lock); in sh73a0_cpg_register_clock()
161 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
173 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in sh73a0_cpg_clocks_init()
175 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
182 spin_lock_init(&cpg->lock); in sh73a0_cpg_clocks_init()
184 cpg->data.clks = clks; in sh73a0_cpg_clocks_init()
185 cpg->data.clk_num = num_clks; in sh73a0_cpg_clocks_init()
203 clk = sh73a0_cpg_register_clock(np, cpg, base, name); in sh73a0_cpg_clocks_init()
[all …]
H A Dclk-r8a73a4.c3 * r8a73a4 Core CPG Clocks
58 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, in r8a73a4_cpg_register_clock() argument
181 table, &cpg->lock); in r8a73a4_cpg_register_clock()
187 struct r8a73a4_cpg *cpg; in r8a73a4_cpg_clocks_init() local
199 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a73a4_cpg_clocks_init()
201 if (cpg == NULL || clks == NULL) { in r8a73a4_cpg_clocks_init()
208 spin_lock_init(&cpg->lock); in r8a73a4_cpg_clocks_init()
210 cpg->data.clks = clks; in r8a73a4_cpg_clocks_init()
211 cpg->data.clk_num = num_clks; in r8a73a4_cpg_clocks_init()
224 clk = r8a73a4_cpg_register_clock(np, cpg, base, name); in r8a73a4_cpg_clocks_init()
[all …]

12345678910