Home
last modified time | relevance | path

Searched full:cpg (Results 1 – 25 of 221) sorted by relevance

123456789

/linux/drivers/clk/renesas/
H A DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
H A Dclk-r8a7740.c3 * r8a7740 Core CPG Clocks
61 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, in r8a7740_cpg_register_clock() argument
139 table, &cpg->lock); in r8a7740_cpg_register_clock()
145 struct r8a7740_cpg *cpg; in r8a7740_cpg_clocks_init() local
160 cpg = kzalloc_obj(*cpg); in r8a7740_cpg_clocks_init()
162 if (cpg == NULL || clks == NULL) { in r8a7740_cpg_clocks_init()
169 spin_lock_init(&cpg->lock); in r8a7740_cpg_clocks_init()
171 cpg->data.clks = clks; in r8a7740_cpg_clocks_init()
172 cpg->data.clk_num = num_clks; in r8a7740_cpg_clocks_init()
185 clk = r8a7740_cpg_register_clock(np, cpg, base, name); in r8a7740_cpg_clocks_init()
[all …]
H A Dclk-sh73a0.c3 * sh73a0 Core CPG Clocks
72 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
155 table, &cpg->lock); in sh73a0_cpg_register_clock()
161 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
173 cpg = kzalloc_obj(*cpg); in sh73a0_cpg_clocks_init()
175 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
182 spin_lock_init(&cpg->lock); in sh73a0_cpg_clocks_init()
184 cpg->data.clks = clks; in sh73a0_cpg_clocks_init()
185 cpg->data.clk_num = num_clks; in sh73a0_cpg_clocks_init()
203 clk = sh73a0_cpg_register_clock(np, cpg, base, name); in sh73a0_cpg_clocks_init()
[all …]
H A Dclk-r8a73a4.c3 * r8a73a4 Core CPG Clocks
60 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, in r8a73a4_cpg_register_clock() argument
183 table, &cpg->lock); in r8a73a4_cpg_register_clock()
189 struct r8a73a4_cpg *cpg; in r8a73a4_cpg_clocks_init() local
201 cpg = kzalloc_obj(*cpg); in r8a73a4_cpg_clocks_init()
203 if (cpg == NULL || clks == NULL) { in r8a73a4_cpg_clocks_init()
210 spin_lock_init(&cpg->lock); in r8a73a4_cpg_clocks_init()
212 cpg->data.clks = clks; in r8a73a4_cpg_clocks_init()
213 cpg->data.clk_num = num_clks; in r8a73a4_cpg_clocks_init()
226 clk = r8a73a4_cpg_register_clock(np, cpg, base, name); in r8a73a4_cpg_clocks_init()
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g057.dtsi8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
81 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
92 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
103 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
114 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
270 clocks = <&cpg CPG_MOD 0x5>;
271 power-domains = <&cpg>;
272 resets = <&cpg 0x36>;
278 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
285 power-domains = <&cpg>;
[all …]
H A Dr9a09g056.dtsi8 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
99 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>;
110 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>;
121 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>;
132 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>;
288 clocks = <&cpg CPG_MOD 0x5>;
289 power-domains = <&cpg>;
290 resets = <&cpg 0x36>;
296 clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>;
303 power-domains = <&cpg>;
[all …]
H A Dr9a09g047.dtsi8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
81 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
92 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
103 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
114 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
265 clocks = <&cpg CPG_MOD 0x5>;
266 power-domains = <&cpg>;
267 resets = <&cpg 0x36>;
273 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
280 power-domains = <&cpg>;
[all …]
H A Dr9a09g011.dtsi9 #include <dt-bindings/clock/r9a09g011-cpg.h>
42 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
[all …]
H A Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
83 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
94 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
153 clocks = <&cpg CPG_MOD 402>;
155 resets = <&cpg 402>;
169 clocks = <&cpg CPG_MOD 912>;
171 resets = <&cpg 912>;
184 clocks = <&cpg CPG_MOD 911>;
186 resets = <&cpg 911>;
199 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a779f0.dtsi8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
122 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
134 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
146 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
158 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
170 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
182 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
194 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
206 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
312 clocks = <&cpg CPG_MOD 907>;
[all …]
H A Dr9a09g077.dtsi8 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
56 clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>;
67 clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>;
78 clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C2>;
89 clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C3>;
133 clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
135 power-domains = <&cpg>;
147 clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
149 power-domains = <&cpg>;
161 clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
[all …]
H A Dr9a09g087.dtsi8 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
56 clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C0>;
67 clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C1>;
78 clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C2>;
89 clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C3>;
133 clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
135 power-domains = <&cpg>;
147 clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
149 power-domains = <&cpg>;
161 clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
[all …]
H A Dr9a07g043u.dtsi28 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
66 clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
67 <&cpg CPG_MOD R9A07G043_CRU_PCLK>,
68 <&cpg CPG_MOD R9A07G043_CRU_ACLK>;
74 resets = <&cpg R9A07G043_CRU_PRESETN>,
75 <&cpg R9A07G043_CRU_ARESETN>;
77 power-domains = <&cpg>;
101 clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
102 <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
103 <&cpg CPG_MOD R9A07G043_CRU_PCLK>;
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
72 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
83 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
134 clocks = <&cpg CPG_MOD 402>;
136 resets = <&cpg 402>;
150 clocks = <&cpg CPG_MOD 912>;
152 resets = <&cpg 912>;
165 clocks = <&cpg CPG_MOD 911>;
167 resets = <&cpg 911>;
180 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
66 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
124 clocks = <&cpg CPG_MOD 402>;
126 resets = <&cpg 402>;
140 clocks = <&cpg CPG_MOD 912>;
142 resets = <&cpg 912>;
155 clocks = <&cpg CPG_MOD 911>;
157 resets = <&cpg 911>;
170 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7744.dtsi10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
46 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
99 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
167 clocks = <&cpg CPG_MOD 402>;
169 resets = <&cpg 402>;
183 clocks = <&cpg CPG_MOD 912>;
185 resets = <&cpg 912>;
198 clocks = <&cpg CPG_MOD 911>;
200 resets = <&cpg 911>;
213 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
85 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
139 clocks = <&cpg CPG_MOD 912>;
141 resets = <&cpg 912>;
154 clocks = <&cpg CPG_MOD 911>;
156 resets = <&cpg 911>;
169 clocks = <&cpg CPG_MOD 910>;
171 resets = <&cpg 910>;
184 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
79 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
101 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
123 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
145 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
167 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
179 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
191 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
203 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
280 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a7742.dtsi8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
57 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
101 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
123 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
145 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
155 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
165 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
175 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
248 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
91 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
152 clocks = <&cpg CPG_MOD 402>;
154 resets = <&cpg 402>;
168 clocks = <&cpg CPG_MOD 912>;
170 resets = <&cpg 912>;
183 clocks = <&cpg CPG_MOD 911>;
185 resets = <&cpg 911>;
198 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr7s9210.dtsi10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
81 clocks = <&cpg CPG_MOD 47>;
83 power-domains = <&cpg>;
98 clocks = <&cpg CPG_MOD 46>;
100 power-domains = <&cpg>;
115 clocks = <&cpg CPG_MOD 45>;
117 power-domains = <&cpg>;
132 clocks = <&cpg CPG_MOD 44>;
134 power-domains = <&cpg>;
149 clocks = <&cpg CPG_MOD 43>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rzv2h-cpg.yaml4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
7 title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
13 On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
21 - renesas,r9a09g047-cpg # RZ/G3E
22 - renesas,r9a09g056-cpg # RZ/V2N
23 - renesas,r9a09g057-cpg # RZ/V2H
48 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
50 <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
83 compatible = "renesas,r9a09g057-cpg";

123456789