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Searched +full:cpg +full:- +full:div6 +full:- +full:clock (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-div6-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas CPG DIV6 Clock
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14 Generator (CPG). Their clock input is divided by a configurable factor from 1
20 - enum:
21 - renesas,r8a73a4-div6-clock # R-Mobile APE6
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/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux/drivers/clk/renesas/
H A Dclk-div6.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_mask: Bitmask covering the register bits to select the parent clock
32 * @nb: Notifier block to save/restore clock state for system resume
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H A Drenesas-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "renesas-cpg-mssr.h"
35 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
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/linux/Documentation/devicetree/bindings/net/can/
H A Drenesas,rcar-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN Controller
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
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/linux/drivers/sh/clk/
H A Dcpg.c2 * Helper routines for SuperH Clock Pulse Generator blocks (CPG).
5 * Copyright (C) 2010 - 2012 Paul Mundt
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
31 void __iomem *mapped_status = (phys_addr_t)clk->status_reg - in sh_clk_read_status()
32 (phys_addr_t)clk->enable_reg + clk->mapped_reg; in sh_clk_read_status()
34 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read_status()
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