2  * Helper routines for SuperH Clock Pulse Generator blocks (CPG).
5  *  Copyright (C) 2010 - 2012  Paul Mundt
21 	if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_read()
22 		return ioread8(clk->mapped_reg);  in sh_clk_read()
23 	else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_read()
24 		return ioread16(clk->mapped_reg);  in sh_clk_read()
26 	return ioread32(clk->mapped_reg);  in sh_clk_read()
31 	void __iomem *mapped_status = (phys_addr_t)clk->status_reg -  in sh_clk_read_status()
32 		(phys_addr_t)clk->enable_reg + clk->mapped_reg;  in sh_clk_read_status()
34 	if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_read_status()
36 	else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_read_status()
44 	if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_write()
45 		iowrite8(value, clk->mapped_reg);  in sh_clk_write()
46 	else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_write()
47 		iowrite16(value, clk->mapped_reg);  in sh_clk_write()
49 		iowrite32(value, clk->mapped_reg);  in sh_clk_write()
54 	sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);  in sh_clk_mstp_enable()
55 	if (clk->status_reg) {  in sh_clk_mstp_enable()
59 		     (sh_clk_read_status(clk) & (1 << clk->enable_bit)) && i;  in sh_clk_mstp_enable()
60 		     i--)  in sh_clk_mstp_enable()
63 			pr_err("cpg: failed to enable %p[%d]\n",  in sh_clk_mstp_enable()
64 			       clk->enable_reg, clk->enable_bit);  in sh_clk_mstp_enable()
65 			return -ETIMEDOUT;  in sh_clk_mstp_enable()
73 	sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk);  in sh_clk_mstp_disable()
90 		clkp->ops = &sh_clk_mstp_clk_ops;  in sh_clk_mstp_register()
102 	return clk->priv;  in clk_to_div_table()
107 	return clk_to_div_table(clk)->div_mult_table;  in clk_to_div_mult_table()
115 	return clk_rate_table_round(clk, clk->freq_table, rate);  in sh_clk_div_round_rate()
123 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div_recalc()
124 			     table, clk->arch_flags ? &clk->arch_flags : NULL);  in sh_clk_div_recalc()
126 	idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;  in sh_clk_div_recalc()
128 	return clk->freq_table[idx].frequency;  in sh_clk_div_recalc()
137 	idx = clk_rate_table_find(clk, clk->freq_table, rate);  in sh_clk_div_set_rate()
142 	value &= ~(clk->div_mask << clk->enable_bit);  in sh_clk_div_set_rate()
143 	value |= (idx << clk->enable_bit);  in sh_clk_div_set_rate()
146 	/* XXX: Should use a post-change notifier */  in sh_clk_div_set_rate()
147 	if (dt->kick)  in sh_clk_div_set_rate()
148 		dt->kick(clk);  in sh_clk_div_set_rate()
155 	if (clk->div_mask == SH_CLK_DIV6_MSK) {  in sh_clk_div_enable()
156 		int ret = sh_clk_div_set_rate(clk, clk->rate);  in sh_clk_div_enable()
173 	 * div6 clocks require the divisor field to be non-zero or the  in sh_clk_div_disable()
177 	if (clk->flags & CLK_MASK_DIV_ON_DISABLE)  in sh_clk_div_disable()
178 		val |= clk->div_mask;  in sh_clk_div_disable()
201 	if (clk->parent)  in sh_clk_init_parent()
204 	if (!clk->parent_table || !clk->parent_num)  in sh_clk_init_parent()
207 	if (!clk->src_width) {  in sh_clk_init_parent()
208 		pr_err("sh_clk_init_parent: cannot select parent clock\n");  in sh_clk_init_parent()
209 		return -EINVAL;  in sh_clk_init_parent()
212 	val  = (sh_clk_read(clk) >> clk->src_shift);  in sh_clk_init_parent()
213 	val &= (1 << clk->src_width) - 1;  in sh_clk_init_parent()
215 	if (val >= clk->parent_num) {  in sh_clk_init_parent()
217 		return -EINVAL;  in sh_clk_init_parent()
220 	clk_reparent(clk, clk->parent_table[val]);  in sh_clk_init_parent()
221 	if (!clk->parent) {  in sh_clk_init_parent()
223 		return -EINVAL;  in sh_clk_init_parent()
234 	int nr_divs = table->div_mult_table->nr_divisors;  in sh_clk_div_register_ops()
243 		return -ENOMEM;  in sh_clk_div_register_ops()
249 		clkp->ops = ops;  in sh_clk_div_register_ops()
250 		clkp->priv = table;  in sh_clk_div_register_ops()
252 		clkp->freq_table = freq_table + (k * freq_table_size);  in sh_clk_div_register_ops()
253 		clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;  in sh_clk_div_register_ops()
264  * div6 support
288 	if (!clk->parent_table || !clk->parent_num)  in sh_clk_div6_set_parent()
289 		return -EINVAL;  in sh_clk_div6_set_parent()
292 	for (i = 0; i < clk->parent_num; i++)  in sh_clk_div6_set_parent()
293 		if (clk->parent_table[i] == parent)  in sh_clk_div6_set_parent()
296 	if (i == clk->parent_num)  in sh_clk_div6_set_parent()
297 		return -ENODEV;  in sh_clk_div6_set_parent()
304 		~(((1 << clk->src_width) - 1) << clk->src_shift);  in sh_clk_div6_set_parent()
306 	sh_clk_write(value | (i << clk->src_shift), clk);  in sh_clk_div6_set_parent()
309 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div6_set_parent()
347 	 * no CLK_ENABLE_ON_INIT means external clock...  in sh_clk_div4_set_parent()
350 	if (parent->flags & CLK_ENABLE_ON_INIT)  in sh_clk_div4_set_parent()
362 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div4_set_parent()
363 			     table, &clk->arch_flags);  in sh_clk_div4_set_parent()
397 /* FSI-DIV */
402 	value = __raw_readl(clk->mapping->base);  in fsidiv_recalc()
406 		return clk->parent->rate;  in fsidiv_recalc()
408 	return clk->parent->rate / value;  in fsidiv_recalc()
418 	__raw_writel(0, clk->mapping->base);  in fsidiv_disable()
425 	value  = __raw_readl(clk->mapping->base) >> 16;  in fsidiv_enable()
429 	__raw_writel((value << 16) | 0x3, clk->mapping->base);  in fsidiv_enable()
438 	idx = (clk->parent->rate / rate) & 0xffff;  in fsidiv_set_rate()
440 		__raw_writel(0, clk->mapping->base);  in fsidiv_set_rate()
442 		__raw_writel(idx << 16, clk->mapping->base);  in fsidiv_set_rate()
465 			return -ENOMEM;  in sh_clk_fsidiv_register()
469 		map->phys		= (phys_addr_t)clks[i].enable_reg;  in sh_clk_fsidiv_register()
470 		map->len		= 8;  in sh_clk_fsidiv_register()