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/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A D	fp_operation.json	5 … "BriefDescription": "This event counts architecturally executed floating-point move operation." 10 …"BriefDescription": "This event counts architecturally executed NOSIMD load operations that using … 15 …"BriefDescription": "This event counts architecturally executed NOSIMD store operations that using… 19 …"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point opera… 23 … "BriefDescription": "This event counts architecturally executed SVE floating-point operation." 27 …"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-poin… 31 …"BriefDescription": "This event counts architecturally executed half-precision floating-point oper… 35 …"BriefDescription": "This event counts architecturally executed Advanced SIMD half-precision float… 39 …"BriefDescription": "This event counts architecturally executed SVE half-precision floating-point … 43 …"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE half-precisio… [all …]
H A D	tlb.json	4 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1I TLB. See L1I_… 8 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1D TLB. See L1D_… 12 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D TLB. See L1D_… 16 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I TLB. See L1I_… 20 …"BriefDescription": "This event counts operations that cause a TLB refill of the L2D TLB. See L2D_… 24 …"BriefDescription": "This event counts operations that cause a TLB access to the L2D TLB. See L2D_… 28 … "BriefDescription": "This event counts data TLB access with at least one translation table walk." 32 …"BriefDescription": "This event counts instruction TLB access with at least one translation table … 37 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 4KB page." 42 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 64KB page." [all …]
H A D	sve.json	4 …"BriefDescription": "This event counts architecturally executed SIMD instructions, excluding the A… 8 …"BriefDescription": "This event counts architecturally executed SVE instructions, including the in… 12 …"BriefDescription": "This event counts architecturally executed SVE instructions, including the in… 16 … "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE operation." 20 "BriefDescription": "This event counts all architecturally executed micro-operation." 24 …"BriefDescription": "This event counts architecturally executed math function operations due to th… 28 …"BriefDescription": "This event counts architecturally executed operations due to scalar, Advanced… 32 …"BriefDescription": "This event counts architecturally executed floating-point fused multiply-add … 36 …"BriefDescription": "This event counts architecturally executed floating-point reciprocal estimate… 40 …"BriefDescription": "This event counts architecturally executed floating-point convert operations … [all …]
H A D	spec_operation.json	4 …"BriefDescription": "This event counts each correction to the predicted program flow that occurs b… 8 …"BriefDescription": "This event counts every branch or other change in the program flow that the b… 12 "BriefDescription": "This event counts every architecturally executed instruction." 16 "BriefDescription": "This event counts every speculatively executed micro-operation." 20 … "BriefDescription": "This event counts architecturally executed load-exclusive instructions." 24 … "BriefDescription": "This event counts architecturally executed store-exclusive instructions." 28 …"BriefDescription": "This event counts architecturally executed memory-reading instructions, as de… 32 …tion": "This event counts architecturally executed memory-writing instructions, as defined by the … 36 …"BriefDescription": "This event counts architecturally executed memory-reading instructions and me… 40 …"BriefDescription": "This event counts architecturally executed integer data-processing instructio… [all …]
H A D	pipeline.json	5 "BriefDescription": "This event counts valid cycles of EAGA pipeline." 10 "BriefDescription": "This event counts valid cycles of EAGB pipeline." 15 "BriefDescription": "This event counts valid cycles of PRX pipeline." 20 "BriefDescription": "This event counts valid cycles of EXA pipeline." 25 "BriefDescription": "This event counts valid cycles of EXB pipeline." 30 "BriefDescription": "This event counts valid cycles of EXC pipeline." 35 "BriefDescription": "This event counts valid cycles of EXD pipeline." 40 "BriefDescription": "This event counts valid cycles of FLA pipeline." 45 "BriefDescription": "This event counts valid cycles of FLB pipeline." 50 "BriefDescription": "This event counts valid cycles of STEA pipeline." [all …]
H A D	l2_cache.json	4 …"BriefDescription": "This event counts operations that cause a cache access to the L2 cache. See L… 8 …"BriefDescription": "This event counts operations that cause a refill of the L2 cache. See L2D_CAC… 12 …"BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 rep… 16 …"BriefDescription": "This event counts operations that cause a TLB refill of the L2I TLB. See L2I_… 20 …"BriefDescription": "This event counts operations that cause a TLB access to the L2I TLB. See L2I_… 24 "BriefDescription": "This event counts L2D_CACHE caused by read access." 28 "BriefDescription": "This event counts L2D_CACHE caused by write access." 32 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by read access." 36 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by write access." 40 …"BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 rep… [all …]
H A D	l3_cache.json	4 …"BriefDescription": "This event counts operations that cause a cache access to the L3 cache, as de… 8 …"BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation… 13 … "BriefDescription": "This event counts operations that cause a cache access to the L3 cache." 18 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access." 23 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access." 28 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access." 33 …"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch or s… 38 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch." 43 …"BriefDescription": "This event counts operations that cause a miss of the L3 cache. Note: This ev… 48 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access." [all …]
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	3 "PublicDescription": "This event counts the occurrence count of the micro-operation split.", 6 "BriefDescription": "This event counts the occurrence count of the micro-operation split." 9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
H A D	pipeline.json	9 "PublicDescription": "This event counts valid cycles of EAGA pipeline.", 12 "BriefDescription": "This event counts valid cycles of EAGA pipeline." 15 "PublicDescription": "This event counts valid cycles of EAGB pipeline.", 18 "BriefDescription": "This event counts valid cycles of EAGB pipeline." 21 "PublicDescription": "This event counts valid cycles of EXA pipeline.", 24 "BriefDescription": "This event counts valid cycles of EXA pipeline." 27 "PublicDescription": "This event counts valid cycles of EXB pipeline.", 30 "BriefDescription": "This event counts valid cycles of EXB pipeline." 33 "PublicDescription": "This event counts valid cycles of FLA pipeline.", 36 "BriefDescription": "This event counts valid cycles of FLA pipeline." [all …]
H A D	cache.json	45 …"PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", 48 … "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." 51 …"PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", 54 … "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." 57 "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.", 60 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." 63 "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", 66 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch." 69 "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", 72 "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." [all …]
/linux/tools/perf/pmu-events/arch/x86/clearwaterforest/
H A D	cache.json	3 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 7 …Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests i… 12 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 16 …Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests in… 21 "BriefDescription": "Counts the number of load ops retired.", 25 "PublicDescription": "Counts the number of load ops retired. Available PDIST counters: 0,1", 30 "BriefDescription": "Counts the number of store ops retired.", 34 … "PublicDescription": "Counts the number of store ops retired. Available PDIST counters: 0,1", 39 …iption": "Counts the number of tagged load uops retired that exceed the latency threshold defined … 45 …iption": "Counts the number of tagged load uops retired that exceed the latency threshold defined … [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A D	cache.json	3 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 7 …: "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door reques… 11 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 15 …ion": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request onl… 20 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p… 24 …on": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request onl… 29 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 33 …Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests i… 38 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 42 …Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests in… [all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	cache.json	3 …"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, s… 7 …"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, … 12 …"BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusi… 16 …"PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclus… 21 …"BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward… 25 …"PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forwar… 30 …"BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Modifie… 34 …"PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modifi… 39 …"BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared … 43 …"PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared… [all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	cache.json	3 …"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, s… 7 …"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, … 12 …"BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusi… 16 …"PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclus… 21 …"BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward… 25 …"PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forwar… 30 …"BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Modifie… 34 …"PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modifi… 39 …"BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared … 43 …"PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared… [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	pipeline.json	3 …"BriefDescription": "Counts the total number of branch instructions retired for all branch types.", 8 …"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP… 12 "BriefDescription": "Counts the number of near CALL branch instructions retired.", 17 …"PublicDescription": "Counts the number of near CALL branch instructions retired. Available PDIST … 22 …"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far … 27 …"PublicDescription": "Counts the number of far branch instructions retired, includes far jump, far… 32 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", 37 …"PublicDescription": "Counts the number of near indirect CALL branch instructions retired. Availab… 42 …"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructio… 47 …"PublicDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructi… [all …]
H A D	cache.json	3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th… 7 …Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due … 11 …"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, s… 15 …"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, … 20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queu… 28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 32 …: "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door reques… 36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 40 …ion": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request onl… [all …]
H A D	memory.json	3 …"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop … 11 "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", 16 …"PublicDescription": "Counts the number of misaligned load uops that are 4K page splits. Available… 21 "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", 26 …"PublicDescription": "Counts the number of misaligned store uops that are 4K page splits. Availabl… 31 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", [all …]
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 11 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 23 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 32 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 41 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 50 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	pipeline.json	3 …"BriefDescription": "Counts the total number of branch instructions retired for all branch types.", 8 …"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP… 12 "BriefDescription": "Counts the number of near CALL branch instructions retired.", 17 …"PublicDescription": "Counts the number of near CALL branch instructions retired. Available PDIST … 22 …"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far … 27 …"PublicDescription": "Counts the number of far branch instructions retired, includes far jump, far… 32 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", 37 …"PublicDescription": "Counts the number of near indirect CALL branch instructions retired. Availab… 42 …"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructio… 47 …"PublicDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructi… [all …]
H A D	cache.json	3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th… 7 …Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due … 11 …"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, s… 15 …"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, … 20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queu… 28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 32 …: "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door reques… 36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 40 …ion": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request onl… [all …]
H A D	memory.json	3 …"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop … 11 "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", 16 …"PublicDescription": "Counts the number of misaligned load uops that are 4K page splits. Available… 21 "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", 26 …"PublicDescription": "Counts the number of misaligned store uops that are 4K page splits. Availabl… 31 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	spec_operation.json	4 "PublicDescription": "Counts branches which are speculatively executed and mispredicted." 8 "PublicDescription": "Counts branches speculatively executed and were predicted right." 12 "PublicDescription": "Counts operations that have been speculatively executed." 16 …"PublicDescription": "Counts micro-operations speculatively executed. This is the count of the num… 20 …"PublicDescription": "Counts unaligned memory read operations issued by the CPU. This event counts… 24 …"PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event count… 28 …"PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unal… 32 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: … 36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … 40 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … [all …]
/linux/tools/perf/util/
H A D	counts.c	6 #include "counts.h" 12 struct perf_counts counts = zalloc(sizeof(counts)); in perf_counts__new() local 14 if (counts) { in perf_counts__new() 19 free(counts); in perf_counts__new() 23 counts->values = values; in perf_counts__new() 27 xyarray__delete(counts->values); in perf_counts__new() 28 free(counts); in perf_counts__new() 32 counts->loaded = values; in perf_counts__new() 35 return counts; in perf_counts__new() 38 void perf_counts__delete(struct perf_counts *counts) in perf_counts__delete() argument [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	spec_operation.json	4 "PublicDescription": "Counts branches which are speculatively executed and mispredicted." 8 "PublicDescription": "Counts branches speculatively executed and were predicted right." 12 "PublicDescription": "Counts operations that have been speculatively executed." 16 …"PublicDescription": "Counts unaligned memory read operations issued by the CPU. This event counts… 20 …"PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event count… 24 …"PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unal… 28 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: … 32 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … 36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … 40 … "PublicDescription": "Counts store-exclusive operations that have been speculatively executed." [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	pipeline.json	3 "BriefDescription": "Counts the number of branch instructions retired (Precise Event)", 11 … "BriefDescription": "Counts the number of near CALL branch instructions retired. (Precise Event)", 20 "BriefDescription": "Counts the number of far branch instructions retired. (Precise Event)", 29 …"BriefDescription": "Counts the number of near indirect CALL branch instructions retired. (Precise… 38 …"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps.… 47 …"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL… 56 …"BriefDescription": "Counts the number of near relative CALL branch instructions retired. (Precise… 65 … "BriefDescription": "Counts the number of near RET branch instructions retired. (Precise Event)", 74 …"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps … 83 …"BriefDescription": "Counts the number of mispredicted branch instructions retired (Precise Event)… [all …]

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