| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | others.json | 20 …e L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, b…
45 …es not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time."
50 …es not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time."
55 …e instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time."
60 …e instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time."
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | mmu.json | 9 …f a Stage 1 translation table walk handled by the MMU. This event is not counted when it is access…
12 …f a Stage 1 translation table walk handled by the MMU. This event is not counted when it is access…
15 …f a Stage 2 translation table walk handled by the MMU. This event is not counted when it is access…
18 …f a Stage 2 translation table walk handled by the MMU. This event is not counted when it is access…
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| /linux/tools/lib/perf/include/internal/ |
| H A D | rc_check.h | 24 * counted structs. It leverages address and leak sanitizers to make sure gets
36 /* Declare a reference counted struct variable. */
41 * reference counted struct.
70 /* Declare a reference counted struct variable. */
75 * reference counted struct.
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | bus.json | 4 …rnal bus, including snoop requests and snoop responses. Each beat of data is counted individually."
12 …unts memory read transactions seen on the external bus. Each beat of data is counted individually."
16 …nts memory write transactions seen on the external bus. Each beat of data is counted individually."
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| H A D | retired.json | 16 "PublicDescription": "Counts architectural writes to TTBR0/1_EL1. If virtualization host extensions are enabled (by setting the HCR_EL2.E2H bit to 1), then accesses to TTBR0/1_EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers are typically updated when the kernel is swapping user-space threads or applications."
20 "PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not. Instructions that explicitly write to the PC are also counted. Note that exception generating instructions, exception return instructions and context synchronization instructions are not counted."
24 "PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a pipeline flush."
|
| H A D | l2_cache.json | 12 "PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line invalidations which do not write data outside the CPU and snoops which return data from an L1 cache are not counted. Data would not be written outside the cache when invalidating a clean cache line."
28 "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
32 "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
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| H A D | l1i_cache.json | 4 …may include accessing multiple instructions, but the single cache line allocation is counted once."
8 …truction cache. Instruction cache accesses caused by cache maintenance operations are not counted."
|
| H A D | l1d_cache.json | 8 "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted."
12 "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode."
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | bus.json | 4 …rnal bus, including snoop requests and snoop responses. Each beat of data is counted individually."
12 …unts memory read transactions seen on the external bus. Each beat of data is counted individually."
16 …nts memory write transactions seen on the external bus. Each beat of data is counted individually."
|
| H A D | retired.json | 16 …EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers …
20 …whether the branch is taken or not. Instructions that explicitly write to the PC are also counted."
24 …"PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a p…
|
| H A D | l2_cache.json | 12 …ta outside the CPU and snoops which return data from an L1 cache are not counted. Data would not b…
28 …ption": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. …
32 …tion": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. …
|
| H A D | l1i_cache.json | 4 …may include accessing multiple instructions, but the single cache line allocation is counted once."
8 …truction cache. Instruction cache accesses caused by cache maintenance operations are not counted."
|
| H A D | l1d_cache.json | 8 …counted including the multiple accesses caused by single instructions such as LDM or STM. Each acc…
12 … or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidati…
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | bus.json | 4 …rnal bus, including snoop requests and snoop responses. Each beat of data is counted individually."
12 …unts memory read transactions seen on the external bus. Each beat of data is counted individually."
16 …nts memory write transactions seen on the external bus. Each beat of data is counted individually."
|
| H A D | retired.json | 16 …EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers …
20 …whether the branch is taken or not. Instructions that explicitly write to the PC are also counted."
24 …"PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a p…
|
| H A D | l2_cache.json | 12 …ta outside the CPU and snoops which return data from an L1 cache are not counted. Data would not b…
28 …ption": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. …
32 …tion": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. …
|
| H A D | l1i_cache.json | 4 …may include accessing multiple instructions, but the single cache line allocation is counted once."
8 …truction cache. Instruction cache accesses caused by cache maintenance operations are not counted."
|
| H A D | l1d_cache.json | 8 …counted including the multiple accesses caused by single instructions such as LDM or STM. Each acc…
12 … or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidati…
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | cache.json | 105 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
108 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
171 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
174 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
177 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
180 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
|
| /linux/Documentation/userspace-api/media/dvb/ |
| H A D | frontend-stat-properties.rst | 116 - ``FE_SCALE_COUNTER`` - Number of error bits counted before the inner
144 - ``FE_SCALE_COUNTER`` - Number of bits counted while measuring
173 - ``FE_SCALE_COUNTER`` - Number of error bits counted after the inner
201 - ``FE_SCALE_COUNTER`` - Number of bits counted while measuring
222 - ``FE_SCALE_COUNTER`` - Number of error blocks counted after the outer
244 - ``FE_SCALE_COUNTER`` - Number of blocks counted while measuring
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| H A D | cache.json | 31 … the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.",
35 …data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted",
39 …ch do not write data outside of the core and snoops which return data from the L1 are not counted",
62 …data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' tr…
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | virtual-memory.json | 36 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
55 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
65 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
|
| /linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| H A D | counters.rst | 21 There are several counter groups based on where the counter is being counted. In
100 and the same traffic is counted in both informative and acceleration counters.
120 counters, except `ptp_tx[i]_packets` is only counted when precision time
129 standard counters which counts it (i.e. accelerated traffic is counted twice).
193 packets are counted: only packets that are in an SKB with a GRO count > 1.
199 packets are counted: only packets that are in an SKB with a GRO count > 1.
204 with a GRO count > 1 are counted.
495 `XDP_TX` action (bouncing). these packets are not counted by other
496 software counters. These packets are counted by physical port and vPort
517 are not counted by other software counters. These packets are counted by
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 156 …le walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 trans…
159 …le walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 trans…
162 … multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 trans…
165 … multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 trans…
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | cache.json | 123 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
126 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
177 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
180 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
183 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
186 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
|