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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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H A Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57-pmu";
25 compatible = "arm,cortex-a57";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
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/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
8 cpu-map {
45 compatible = "arm,cortex-a57";
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
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/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dsilicon-errata.txt1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
55 相應的內核配置（Kconfig）選項被加在 “內核特性（Kernel Features）”->
66 +----------------+-----------------+-----------------+-------------------------+
67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
69 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dsilicon-errata.txt1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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/linux/tools/perf/pmu-events/arch/arm64/
H A Dmapfile.csv10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd020,v1,arm/cortex-a34,core
16 0x00000000410fd030,v1,arm/cortex-a53,core
17 0x00000000420f1000,v1,arm/cortex-a53,core
18 0x00000000410fd040,v1,arm/cortex-a3
[all...]
/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 interrupt-parent = <&gic>;
43 #address-cells = <2>;
44 #size-cells = <2>;
47 #address-cells = <2>;
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/linux/arch/arm64/boot/dts/arm/
H A Djuno.dts4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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H A Djuno-r1.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
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/linux/drivers/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
106 combination of Denver and Cortex-A57 CPU cores and a GPU based on
107 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
109 multi-format support, ISP for image capture processing and BPMP for
/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
279 ARM 64-bit (AArch64) Linux support.
287 # required due to use of the -Zfixed-x18 flag.
290 # -Zsanitizer=shadow-call-stack flag.
300 depends on $(cc-option,-fpatchable-function-entry=2)
326 # VA_BITS - PAGE_SHIFT - 3
404 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
409 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
459 at stage-2.
467 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
30 arm-pmu {
31 compatible = "arm,cortex-a57-pmu";
36 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
42 compatible = "fixed-clock";
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H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
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/linux/arch/arm64/kernel/
H A Dcpu_errata.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
24 if (!is_midr_in_range(midr, &entry->midr_range)) in is_affected_midr_range()
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) in is_affected_midr_range()
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mas in is_affected_midr_range()
[all...]
/linux/Documentation/arch/arm64/
H A Dsilicon-errata.rst10 so-called "errata", which can cause it to deviate from the architecture
32 cases (e.g. those cases that both require a non-secure workaround *and*
37 Features" -> "ARM errata workarounds via the alternatives framework".
40 detected. For less-intrusive workarounds, a Kconfig option is not
50 +----------------+-----------------+-----------------+-----------------------------+
54 +----------------+-----------------+-----------------+-----------------------------+
55 +----------------+-----------------+-----------------+-----------------------------+
57 +----------------+-----------------+-----------------+-----------------------------+
59 +----------------+-----------------+-----------------+-----------------------------+
60 +----------------+-----------------+-----------------+-----------------------------+
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
49 - const: arm,vexpress,v2p-ca9
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/linux/Documentation/driver-api/thermal/
H A Dcpu-cooling-api.rst22 --------------------------------------------
30 "thermal-cpufreq-%x". This api can support multiple instances of cpufreq
42 the name "thermal-cpufreq-%x" linking it with a device tree node, in
54 This interface function unregisters the "thermal-cpufreq-%x" cooling device.
63 supported currently). This power model requires that the operating-points of
73 - The time the processor spends running, consuming dynamic power, as
76 - The voltage and frequency levels as a result of DVFS. The DVFS
78 - In running time the 'execution' behaviour (instruction types, memory
91 The detailed behaviour for f(run) could be modelled on-line. However,
92 in practice, such an on-line model has dependencies on a number of
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/linux/Documentation/devicetree/bindings/dvfs/
H A Dperformance-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
30 \#performance-domain-cells property in the performance domain provider node.
35 "#performance-domain-cells":
44 performance-domains:
45 $ref: /schemas/types.yaml#/definitions/phandle-array
53 - |
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/linux/arch/arm/mm/
H A Dproc-v7-bugs.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/arm-smccc.h>
8 #include <asm/proc-fns.h>
152 /* Cortex A57/A72 require firmware workaround */ in cpu_v7_spectre_v2_init()
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5433-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "oscclk" - PLL input clock from XXTI
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]

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