Searched +full:corepwm +full:- +full:rtl +full:- +full:v4 (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Microchip IP corePWM controller11 - Conor Dooley <conor.dooley@microchip.com>14 corePWM is an 16 channel pulse width modulator FPGA IP16 https://www.microsemi.com/existing-parts/parts/15211819 - $ref: pwm.yaml#24 - const: microchip,corepwm-rtl-v4[all …]
1 // SPDX-License-Identifier: GPL-2.03 * corePWM driver for Microchip "soft" FPGA IP cores.5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb11 * - If the IP block is configured without "shadow registers", all register19 * - The IP block has no concept of a duty cycle, only rising/falling edges of28 * - The PWM period is set for the whole IP block not per channel. The driver76 * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg in mchp_core_pwm_enable()79 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); in mchp_core_pwm_enable()80 shift = pwm->hwpwm & 7; in mchp_core_pwm_enable()[all …]