1 // SPDX-License-Identifier: GPL-2.0
3  * corePWM driver for Microchip "soft" FPGA IP cores.
5  * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8  * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11  * - If the IP block is configured without "shadow registers", all register
19  * - The IP block has no concept of a duty cycle, only rising/falling edges of
28  * - The PWM period is set for the whole IP block not per channel. The driver
76 	 * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg  in mchp_core_pwm_enable()
79 	reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);  in mchp_core_pwm_enable()
80 	shift = pwm->hwpwm & 7;  in mchp_core_pwm_enable()
82 	channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);  in mchp_core_pwm_enable()
86 	writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);  in mchp_core_pwm_enable()
87 	mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);  in mchp_core_pwm_enable()
88 	mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;  in mchp_core_pwm_enable()
93 	 * This is a NO-OP if the channel does not have shadow registers.  in mchp_core_pwm_enable()
95 	if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))  in mchp_core_pwm_enable()
96 		mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);  in mchp_core_pwm_enable()
110 	if (mchp_core_pwm->sync_update_mask & (1 << channel)) {  in mchp_core_pwm_wait_for_sync_update()
115 		remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp,  in mchp_core_pwm_wait_for_sync_update()
143 	duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp);  in mchp_core_pwm_calc_duty()
165 	if (state->polarity == PWM_POLARITY_INVERSED) {  in mchp_core_pwm_apply_duty()
178 	writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));  in mchp_core_pwm_apply_duty()
179 	writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));  in mchp_core_pwm_apply_duty()
192 	 * period = -------------------------------------  in mchp_core_pwm_calc_period()
207 	 * neg-/pos-edge issue described in the limitations.  in mchp_core_pwm_calc_period()
209 	tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);  in mchp_core_pwm_calc_period()
240 		return -EINVAL;  in mchp_core_pwm_calc_period()
247 	 * prescale = ------------------------- - 1  in mchp_core_pwm_calc_period()
252 	 * ------------------- was precomputed as `tmp`  in mchp_core_pwm_calc_period()
255 	*prescale = ((u16)tmp) / (MCHPCOREPWM_PERIOD_STEPS_MAX + 1) - 1;  in mchp_core_pwm_calc_period()
260 	 * period_steps = ----------------------------- - 1  in mchp_core_pwm_calc_period()
281 	if (!state->enabled) {  in mchp_core_pwm_apply_locked()
282 		mchp_core_pwm_enable(chip, pwm, false, pwm->state.period);  in mchp_core_pwm_apply_locked()
291 	clk_rate = clk_get_rate(mchp_core_pwm->clk);  in mchp_core_pwm_apply_locked()
293 		return -EINVAL;  in mchp_core_pwm_apply_locked()
308 	period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);  in mchp_core_pwm_apply_locked()
314 		hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_apply_locked()
315 		hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_apply_locked()
319 			return -EINVAL;  in mchp_core_pwm_apply_locked()
329 			return -EINVAL;  in mchp_core_pwm_apply_locked()
346 		writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_apply_locked()
347 		writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_apply_locked()
352 	mchp_core_pwm_enable(chip, pwm, true, pwm->state.period);  in mchp_core_pwm_apply_locked()
362 	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);  in mchp_core_pwm_apply()
375 	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);  in mchp_core_pwm_get_state()
377 	if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))  in mchp_core_pwm_get_state()
378 		state->enabled = true;  in mchp_core_pwm_get_state()
380 		state->enabled = false;  in mchp_core_pwm_get_state()
382 	rate = clk_get_rate(mchp_core_pwm->clk);  in mchp_core_pwm_get_state()
389 	 * period = -------------------------------------  in mchp_core_pwm_get_state()
397 	prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_get_state()
398 	period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_get_state()
400 	state->period = (period_steps + 1) * (prescale + 1);  in mchp_core_pwm_get_state()
401 	state->period *= NSEC_PER_SEC;  in mchp_core_pwm_get_state()
402 	state->period = DIV64_U64_ROUND_UP(state->period, rate);  in mchp_core_pwm_get_state()
404 	posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));  in mchp_core_pwm_get_state()
405 	negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));  in mchp_core_pwm_get_state()
408 		state->duty_cycle = state->period;  in mchp_core_pwm_get_state()
409 		state->period *= 2;  in mchp_core_pwm_get_state()
411 		duty_steps = abs((s16)posedge - (s16)negedge);  in mchp_core_pwm_get_state()
412 		state->duty_cycle = duty_steps * (prescale + 1) * NSEC_PER_SEC;  in mchp_core_pwm_get_state()
413 		state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle, rate);  in mchp_core_pwm_get_state()
416 	state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;  in mchp_core_pwm_get_state()
428 		.compatible = "microchip,corepwm-rtl-v4",
441 	chip = devm_pwmchip_alloc(&pdev->dev, 16, sizeof(*mchp_core_pwm));  in mchp_core_pwm_probe()
446 	mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);  in mchp_core_pwm_probe()
447 	if (IS_ERR(mchp_core_pwm->base))  in mchp_core_pwm_probe()
448 		return PTR_ERR(mchp_core_pwm->base);  in mchp_core_pwm_probe()
450 	mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);  in mchp_core_pwm_probe()
451 	if (IS_ERR(mchp_core_pwm->clk))  in mchp_core_pwm_probe()
452 		return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk),  in mchp_core_pwm_probe()
455 	if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask",  in mchp_core_pwm_probe()
456 				 &mchp_core_pwm->sync_update_mask))  in mchp_core_pwm_probe()
457 		mchp_core_pwm->sync_update_mask = 0;  in mchp_core_pwm_probe()
459 	chip->ops = &mchp_core_pwm_ops;  in mchp_core_pwm_probe()
461 	mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));  in mchp_core_pwm_probe()
462 	mchp_core_pwm->channel_enabled |=  in mchp_core_pwm_probe()
463 		readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;  in mchp_core_pwm_probe()
469 	writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);  in mchp_core_pwm_probe()
470 	mchp_core_pwm->update_timestamp = ktime_get();  in mchp_core_pwm_probe()
472 	ret = devm_pwmchip_add(&pdev->dev, chip);  in mchp_core_pwm_probe()
474 		return dev_err_probe(&pdev->dev, ret, "Failed to add pwmchip\n");  in mchp_core_pwm_probe()
481 		.name = "mchp-core-pwm",
490 MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs");