1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Arasan SDHCI Controller 8 9maintainers: 10 - Adrian Hunter <adrian.hunter@intel.com> 11 12allOf: 13 - $ref: mmc-controller.yaml# 14 - if: 15 properties: 16 compatible: 17 contains: 18 const: arasan,sdhci-5.1 19 then: 20 required: 21 - phys 22 - phy-names 23 - if: 24 properties: 25 compatible: 26 contains: 27 enum: 28 - xlnx,zynqmp-8.9a 29 - xlnx,versal-8.9a 30 - xlnx,versal-net-emmc 31 then: 32 properties: 33 clock-output-names: 34 oneOf: 35 - items: 36 - const: clk_out_sd0 37 - const: clk_in_sd0 38 - items: 39 - const: clk_out_sd1 40 - const: clk_in_sd1 41 - if: 42 properties: 43 compatible: 44 contains: 45 const: renesas,rzn1-sdhci 46 then: 47 properties: 48 interrupts: 49 minItems: 2 50 51properties: 52 compatible: 53 oneOf: 54 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY 55 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY 56 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY 57 - items: 58 - const: renesas,r9a06g032-sdhci # Renesas RZ/N1D SoC 59 - const: renesas,rzn1-sdhci # Renesas RZ/N1 family 60 - const: arasan,sdhci-8.9a 61 - items: 62 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY 63 - const: arasan,sdhci-5.1 64 description: 65 For this device it is strongly suggested to include 66 arasan,soc-ctl-syscon. 67 - items: 68 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY 69 - const: arasan,sdhci-8.9a 70 description: 71 For this device it is strongly suggested to include 72 clock-output-names and '#clock-cells'. 73 - items: 74 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY 75 - const: arasan,sdhci-8.9a 76 description: 77 For this device it is strongly suggested to include 78 clock-output-names and '#clock-cells'. 79 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY 80 description: 81 For this device it is strongly suggested to include 82 clock-output-names and '#clock-cells'. 83 - items: 84 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY 85 - const: arasan,sdhci-5.1 86 description: 87 For this device it is strongly suggested to include 88 arasan,soc-ctl-syscon. 89 - items: 90 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY 91 - const: arasan,sdhci-5.1 92 description: 93 For this device it is strongly suggested to include 94 arasan,soc-ctl-syscon. 95 - items: 96 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY 97 - const: arasan,sdhci-5.1 98 description: 99 For this device it is strongly suggested to include 100 arasan,soc-ctl-syscon. 101 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller 102 description: 103 For this device it is strongly suggested to include 104 arasan,soc-ctl-syscon. 105 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller 106 description: 107 For this device it is strongly suggested to include 108 arasan,soc-ctl-syscon. 109 110 reg: 111 maxItems: 1 112 113 clocks: 114 minItems: 2 115 maxItems: 3 116 117 clock-names: 118 minItems: 2 119 items: 120 - const: clk_xin 121 - const: clk_ahb 122 - const: gate 123 124 interrupts: 125 minItems: 1 126 maxItems: 2 127 128 interrupt-names: 129 minItems: 1 130 items: 131 - const: int 132 - const: wakeup 133 134 phys: 135 maxItems: 1 136 137 phy-names: 138 const: phy_arasan 139 140 resets: 141 maxItems: 1 142 143 arasan,soc-ctl-syscon: 144 $ref: /schemas/types.yaml#/definitions/phandle 145 description: 146 A phandle to a syscon device (see ../mfd/syscon.txt) used to access 147 core corecfg registers. Offsets of registers in this syscon are 148 determined based on the main compatible string for the device. 149 150 clock-output-names: 151 minItems: 1 152 maxItems: 2 153 description: 154 Name of the card clock which will be exposed by this device. 155 156 '#clock-cells': 157 enum: [0, 1] 158 description: 159 With this property in place we will export one or two clocks 160 representing the Card Clock. These clocks are expected to be 161 consumed by our PHY. 162 163 xlnx,fails-without-test-cd: 164 $ref: /schemas/types.yaml#/definitions/flag 165 description: 166 When present, the controller doesn't work when the CD line is not 167 connected properly, and the line is not connected properly. 168 Test mode can be used to force the controller to function. 169 170 xlnx,int-clock-stable-broken: 171 $ref: /schemas/types.yaml#/definitions/flag 172 description: 173 When present, the controller always reports that the internal clock 174 is stable even when it is not. 175 176 xlnx,mio-bank: 177 $ref: /schemas/types.yaml#/definitions/uint32 178 enum: [0, 1, 2] 179 default: 0 180 description: 181 The MIO bank number in which the command and data lines are configured. 182 183 iommus: 184 maxItems: 1 185 186 power-domains: 187 maxItems: 1 188 189dependencies: 190 '#clock-cells': [ clock-output-names ] 191 192required: 193 - compatible 194 - reg 195 - interrupts 196 - clocks 197 - clock-names 198 199unevaluatedProperties: false 200 201examples: 202 - | 203 mmc@e0100000 { 204 compatible = "arasan,sdhci-8.9a"; 205 reg = <0xe0100000 0x1000>; 206 clock-names = "clk_xin", "clk_ahb"; 207 clocks = <&clkc 21>, <&clkc 32>; 208 interrupt-parent = <&gic>; 209 interrupts = <0 24 4>; 210 }; 211 212 - | 213 mmc@e2800000 { 214 compatible = "arasan,sdhci-5.1"; 215 reg = <0xe2800000 0x1000>; 216 clock-names = "clk_xin", "clk_ahb"; 217 clocks = <&cru 8>, <&cru 18>; 218 interrupt-parent = <&gic>; 219 interrupts = <0 24 4>; 220 phys = <&emmc_phy>; 221 phy-names = "phy_arasan"; 222 }; 223 224 - | 225 #include <dt-bindings/clock/rk3399-cru.h> 226 #include <dt-bindings/interrupt-controller/arm-gic.h> 227 #include <dt-bindings/interrupt-controller/irq.h> 228 mmc@fe330000 { 229 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 230 reg = <0xfe330000 0x10000>; 231 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 233 clock-names = "clk_xin", "clk_ahb"; 234 arasan,soc-ctl-syscon = <&grf>; 235 assigned-clocks = <&cru SCLK_EMMC>; 236 assigned-clock-rates = <200000000>; 237 clock-output-names = "emmc_cardclock"; 238 phys = <&emmc_phy>; 239 phy-names = "phy_arasan"; 240 #clock-cells = <0>; 241 }; 242 243 - | 244 mmc@ff160000 { 245 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 246 interrupt-parent = <&gic>; 247 interrupts = <0 48 4>; 248 reg = <0xff160000 0x1000>; 249 clocks = <&clk200>, <&clk200>, <&clk1200>; 250 clock-names = "clk_xin", "clk_ahb", "gate"; 251 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 252 #clock-cells = <1>; 253 clk-phase-sd-hs = <63>, <72>; 254 }; 255 256 - | 257 mmc@f1040000 { 258 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; 259 interrupt-parent = <&gic>; 260 interrupts = <0 126 4>; 261 reg = <0xf1040000 0x10000>; 262 clocks = <&clk200>, <&clk200>, <&clk1200>; 263 clock-names = "clk_xin", "clk_ahb", "gate"; 264 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 265 #clock-cells = <1>; 266 clk-phase-sd-hs = <132>, <60>; 267 }; 268 269 - | 270 #define LGM_CLK_EMMC5 271 #define LGM_CLK_NGI 272 #define LGM_GCLK_EMMC 273 mmc@ec700000 { 274 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1"; 275 reg = <0xec700000 0x300>; 276 interrupt-parent = <&ioapic1>; 277 interrupts = <44 1>; 278 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>, 279 <&cgu0 LGM_GCLK_EMMC>; 280 clock-names = "clk_xin", "clk_ahb", "gate"; 281 clock-output-names = "emmc_cardclock"; 282 #clock-cells = <0>; 283 phys = <&emmc_phy>; 284 phy-names = "phy_arasan"; 285 arasan,soc-ctl-syscon = <&sysconf>; 286 }; 287 288 - | 289 #define LGM_CLK_SDIO 290 #define LGM_GCLK_SDXC 291 mmc@ec600000 { 292 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1"; 293 reg = <0xec600000 0x300>; 294 interrupt-parent = <&ioapic1>; 295 interrupts = <43 1>; 296 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>, 297 <&cgu0 LGM_GCLK_SDXC>; 298 clock-names = "clk_xin", "clk_ahb", "gate"; 299 clock-output-names = "sdxc_cardclock"; 300 #clock-cells = <0>; 301 phys = <&sdxc_phy>; 302 phy-names = "phy_arasan"; 303 arasan,soc-ctl-syscon = <&sysconf>; 304 }; 305 306 - | 307 #define KEEM_BAY_PSS_AUX_EMMC 308 #define KEEM_BAY_PSS_EMMC 309 mmc@33000000 { 310 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1"; 311 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 312 reg = <0x33000000 0x300>; 313 clock-names = "clk_xin", "clk_ahb"; 314 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>, 315 <&scmi_clk KEEM_BAY_PSS_EMMC>; 316 phys = <&emmc_phy>; 317 phy-names = "phy_arasan"; 318 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>; 319 assigned-clock-rates = <200000000>; 320 clock-output-names = "emmc_cardclock"; 321 #clock-cells = <0>; 322 arasan,soc-ctl-syscon = <&mmc_phy_syscon>; 323 }; 324 325 - | 326 #define KEEM_BAY_PSS_AUX_SD0 327 #define KEEM_BAY_PSS_SD0 328 mmc@31000000 { 329 compatible = "intel,keembay-sdhci-5.1-sd"; 330 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 331 reg = <0x31000000 0x300>; 332 clock-names = "clk_xin", "clk_ahb"; 333 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>, 334 <&scmi_clk KEEM_BAY_PSS_SD0>; 335 arasan,soc-ctl-syscon = <&sd0_phy_syscon>; 336 }; 337