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Searched full:core_clk (Results 1 – 25 of 105) sorted by relevance

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/linux/arch/arc/boot/dts/
H A Dskeleton_hs_idu.dtsi21 clocks = <&core_clk>;
27 clocks = <&core_clk>;
33 clocks = <&core_clk>;
39 clocks = <&core_clk>;
48 clocks = <&core_clk>;
54 clocks = <&core_clk>;
H A Dskeleton_hs.dtsi21 clocks = <&core_clk>;
30 clocks = <&core_clk>;
36 clocks = <&core_clk>;
42 clocks = <&core_clk>;
H A Dhsdk.dts37 clocks = <&core_clk>;
44 clocks = <&core_clk>;
51 clocks = <&core_clk>;
58 clocks = <&core_clk>;
100 clocks = <&core_clk>;
106 clocks = <&core_clk>;
123 core_clk: core-clk@0 { label
134 assigned-clocks = <&core_clk>;
H A Dskeleton.dtsi26 clocks = <&core_clk>;
35 clocks = <&core_clk>;
41 clocks = <&core_clk>;
H A Dnsim_700.dts32 core_clk: core_clk { label
H A Dvdk_axc003.dtsi24 core_clk: core_clk { label
H A Dvdk_axc003_idu.dtsi25 core_clk: core_clk { label
H A Dhaps_hs_idu.dts37 core_clk: core_clk { label
H A Dnsimosci.dts35 core_clk: core_clk { label
/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpllcore.c3 * DPLL + CORE_CLK composite clock functions
44 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
46 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
54 long long core_clk; in omap2xxx_clk_get_core_rate() local
59 core_clk = omap2_get_dpll_rate(dpll_core_ck); in omap2xxx_clk_get_core_rate()
64 core_clk = 32768; in omap2xxx_clk_get_core_rate()
66 core_clk *= v; in omap2xxx_clk_get_core_rate()
68 return core_clk; in omap2xxx_clk_get_core_rate()
/linux/arch/arm/boot/dts/marvell/
H A Dorion5x.dtsi28 clocks = <&core_clk 0>;
38 clocks = <&core_clk 0>;
48 clocks = <&core_clk 0>;
58 clocks = <&core_clk 0>;
94 clocks = <&core_clk 0>;
103 clocks = <&core_clk 0>;
112 clocks = <&core_clk 0>;
137 clocks = <&core_clk 0>;
145 clocks = <&core_clk 0>;
H A Ddove.dtsi185 clocks = <&core_clk 0>;
198 clocks = <&core_clk 0>;
207 clocks = <&core_clk 0>;
216 clocks = <&core_clk 0>;
227 clocks = <&core_clk 0>;
236 clocks = <&core_clk 0>;
247 clocks = <&core_clk 0>;
282 clocks = <&core_clk 0>;
290 clocks = <&core_clk 0>;
482 clocks = <&core_clk 0>;
[all …]
H A Dkirkwood.dtsi21 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
122 core_clk: core-clocks@10030 { label
222 clocks = <&core_clk 0>;
243 clocks = <&core_clk 0>;
/linux/drivers/i2c/busses/
H A Di2c-npcm7xx.c267 u32 core_clk; member
278 .core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x4,
283 .core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x1,
288 .core_clk = 50000000, .hldt = 0x2A, .dbcnt = 0x1,
293 .core_clk = 48000000, .hldt = 0x2A, .dbcnt = 0x1,
298 .core_clk = 40000000, .hldt = 0x2A, .dbcnt = 0x1,
303 .core_clk = 30000000, .hldt = 0x2A, .dbcnt = 0x1,
308 .core_clk = 29000000, .hldt = 0x2A, .dbcnt = 0x1,
313 .core_clk = 26000000, .hldt = 0x2A, .dbcnt = 0x1,
318 .core_clk = 25000000, .hldt = 0x2A, .dbcnt = 0x1,
[all …]
/linux/drivers/soc/qcom/
H A Docmem.c59 struct clk *core_clk; member
311 ocmem->core_clk = devm_clk_get(dev, "core"); in ocmem_dev_probe()
312 if (IS_ERR(ocmem->core_clk)) in ocmem_dev_probe()
313 return dev_err_probe(dev, PTR_ERR(ocmem->core_clk), in ocmem_dev_probe()
334 WARN_ON(clk_set_rate(ocmem->core_clk, 1000) < 0); in ocmem_dev_probe()
336 ret = clk_prepare_enable(ocmem->core_clk); in ocmem_dev_probe()
342 clk_disable_unprepare(ocmem->core_clk); in ocmem_dev_probe()
409 clk_disable_unprepare(ocmem->core_clk); in ocmem_dev_probe()
418 clk_disable_unprepare(ocmem->core_clk); in ocmem_dev_remove()
H A Dice.c97 struct clk *core_clk; member
279 err = clk_prepare_enable(ice->core_clk); in qcom_ice_resume()
292 clk_disable_unprepare(ice->core_clk); in qcom_ice_suspend()
544 engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); in qcom_ice_create()
545 if (!engine->core_clk) in qcom_ice_create()
546 engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); in qcom_ice_create()
547 if (!engine->core_clk) in qcom_ice_create()
548 engine->core_clk = devm_clk_get_enabled(dev, NULL); in qcom_ice_create()
549 if (IS_ERR(engine->core_clk)) in qcom_ice_create()
550 return ERR_CAST(engine->core_clk); in qcom_ice_create()
/linux/Documentation/devicetree/bindings/ufs/
H A Dqcom,ufs.yaml134 - const: core_clk
170 - const: core_clk
199 - const: core_clk
229 - const: core_clk
259 - const: core_clk
334 clock-names = "core_clk",
H A Dcdns,ufshc.yaml42 - const: core_clk
72 clock-names = "core_clk", "phy_clk";
/linux/drivers/char/hw_random/
H A Dmeson-rng.c90 struct clk *core_clk; in meson_rng_probe() local
105 core_clk = devm_clk_get_optional_enabled(dev, "core"); in meson_rng_probe()
106 if (IS_ERR(core_clk)) in meson_rng_probe()
107 return dev_err_probe(dev, PTR_ERR(core_clk), in meson_rng_probe()
/linux/Documentation/devicetree/bindings/media/
H A Dallegro,al5e.yaml53 - const: core_clk
83 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
100 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
/linux/drivers/watchdog/
H A Dstarfive-wdt.c104 struct clk *core_clk; member
154 ret = clk_prepare_enable(wdt->core_clk); in starfive_wdt_enable_clock()
165 clk_disable_unprepare(wdt->core_clk); in starfive_wdt_disable_clock()
177 wdt->core_clk = devm_clk_get(dev, "core"); in starfive_wdt_get_clock()
178 if (IS_ERR(wdt->core_clk)) in starfive_wdt_get_clock()
179 return dev_err_probe(dev, PTR_ERR(wdt->core_clk), "failed to get core clock\n"); in starfive_wdt_get_clock()
469 wdt->freq = clk_get_rate(wdt->core_clk); in starfive_wdt_probe()
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dkirkwood.txt25 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
/linux/Documentation/devicetree/bindings/misc/
H A Dxlnx,sd-fec.yaml48 - const: core_clk
52 - core_clk
130 clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk",
/linux/drivers/gpio/
H A Dgpio-spacemit-k1.c242 struct clk *core_clk, *bus_clk; in spacemit_gpio_probe() local
260 core_clk = devm_clk_get_enabled(dev, "core"); in spacemit_gpio_probe()
261 if (IS_ERR(core_clk)) in spacemit_gpio_probe()
262 return dev_err_probe(dev, PTR_ERR(core_clk), "failed to get clock\n"); in spacemit_gpio_probe()
/linux/drivers/mmc/host/
H A Dmeson-mx-sdio.c105 struct clk *core_clk; member
678 host->core_clk = devm_clk_get(host->controller_dev, "core"); in meson_mx_mmc_probe()
679 if (IS_ERR(host->core_clk)) { in meson_mx_mmc_probe()
680 ret = PTR_ERR(host->core_clk); in meson_mx_mmc_probe()
694 ret = clk_prepare_enable(host->core_clk); in meson_mx_mmc_probe()
724 clk_disable_unprepare(host->core_clk); in meson_mx_mmc_probe()
744 clk_disable_unprepare(host->core_clk); in meson_mx_mmc_remove()

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