| /linux/arch/arc/boot/dts/ |
| H A D | skeleton_hs_idu.dtsi | 21 clocks = <&core_clk>;
27 clocks = <&core_clk>;
33 clocks = <&core_clk>;
39 clocks = <&core_clk>;
48 clocks = <&core_clk>;
54 clocks = <&core_clk>;
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| H A D | skeleton_hs.dtsi | 21 clocks = <&core_clk>;
30 clocks = <&core_clk>;
36 clocks = <&core_clk>;
42 clocks = <&core_clk>;
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| H A D | hsdk.dts | 37 clocks = <&core_clk>;
44 clocks = <&core_clk>;
51 clocks = <&core_clk>;
58 clocks = <&core_clk>;
100 clocks = <&core_clk>;
106 clocks = <&core_clk>;
123 core_clk: core-clk@0 { label
134 assigned-clocks = <&core_clk>;
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| H A D | skeleton.dtsi | 26 clocks = <&core_clk>;
35 clocks = <&core_clk>;
41 clocks = <&core_clk>;
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| H A D | nsim_700.dts | 32 core_clk: core_clk { label
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| H A D | vdk_axc003.dtsi | 24 core_clk: core_clk { label
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| H A D | vdk_axc003_idu.dtsi | 25 core_clk: core_clk { label
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| H A D | haps_hs_idu.dts | 37 core_clk: core_clk { label
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| H A D | nsimosci.dts | 35 core_clk: core_clk { label
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| H A D | nsimosci_hs.dts | 35 core_clk: core_clk { label
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| H A D | haps_hs.dts | 40 core_clk: core_clk { label
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| H A D | nsimosci_hs_idu.dts | 33 core_clk: core_clk { label
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| H A D | axc001.dtsi | 25 core_clk: core_clk { label
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| /linux/arch/arm/mach-omap2/ |
| H A D | clkt2xxx_dpllcore.c | 3 * DPLL + CORE_CLK composite clock functions
44 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
46 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
54 long long core_clk; in omap2xxx_clk_get_core_rate() local
59 core_clk = omap2_get_dpll_rate(dpll_core_ck); in omap2xxx_clk_get_core_rate()
64 core_clk = 32768; in omap2xxx_clk_get_core_rate()
66 core_clk *= v; in omap2xxx_clk_get_core_rate()
68 return core_clk; in omap2xxx_clk_get_core_rate()
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| H A D | sdrc2xxx.c | 72 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
73 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | orion5x.dtsi | 28 clocks = <&core_clk 0>;
38 clocks = <&core_clk 0>;
48 clocks = <&core_clk 0>;
58 clocks = <&core_clk 0>;
94 clocks = <&core_clk 0>;
103 clocks = <&core_clk 0>;
112 clocks = <&core_clk 0>;
137 clocks = <&core_clk 0>;
145 clocks = <&core_clk 0>;
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| H A D | dove.dtsi | 185 clocks = <&core_clk 0>;
198 clocks = <&core_clk 0>;
207 clocks = <&core_clk 0>;
216 clocks = <&core_clk 0>;
227 clocks = <&core_clk 0>;
236 clocks = <&core_clk 0>;
247 clocks = <&core_clk 0>;
282 clocks = <&core_clk 0>;
290 clocks = <&core_clk 0>;
482 clocks = <&core_clk 0>;
[all …]
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| H A D | kirkwood.dtsi | 21 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
122 core_clk: core-clocks@10030 { label
222 clocks = <&core_clk 0>;
243 clocks = <&core_clk 0>;
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-intel-gw.c | 65 struct clk *core_clk; member
217 pcie->core_clk = devm_clk_get(dev, NULL); in intel_pcie_get_resources()
218 if (IS_ERR(pcie->core_clk)) { in intel_pcie_get_resources()
219 ret = PTR_ERR(pcie->core_clk); in intel_pcie_get_resources()
306 ret = clk_prepare_enable(pcie->core_clk); in intel_pcie_host_setup()
327 clk_disable_unprepare(pcie->core_clk); in intel_pcie_host_setup()
338 clk_disable_unprepare(pcie->core_clk); in __intel_pcie_remove()
363 clk_disable_unprepare(pcie->core_clk); in intel_pcie_suspend_noirq()
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| /linux/drivers/char/hw_random/ |
| H A D | meson-rng.c | 90 struct clk *core_clk; in meson_rng_probe() local
105 core_clk = devm_clk_get_optional_enabled(dev, "core"); in meson_rng_probe()
106 if (IS_ERR(core_clk)) in meson_rng_probe()
107 return dev_err_probe(dev, PTR_ERR(core_clk), in meson_rng_probe()
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | allegro,al5e.yaml | 53 - const: core_clk
83 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
100 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
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| /linux/Documentation/devicetree/bindings/ufs/ |
| H A D | qcom,ufs.yaml | 80 - const: core_clk
109 - const: core_clk
138 - const: core_clk
221 clock-names = "core_clk",
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| H A D | cdns,ufshc.yaml | 42 - const: core_clk
72 clock-names = "core_clk", "phy_clk";
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| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | xlnx,sd-fec.yaml | 48 - const: core_clk
52 - core_clk
130 clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk",
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| /linux/drivers/ufs/host/ |
| H A D | cdns-pltfrm.c | 104 * cdns_ufs_set_hclkdiv() - set HCLKDIV register value based on the core_clk.
122 if (!strcmp(clki->name, "core_clk")) in cdns_ufs_set_hclkdiv()
127 dev_err(hba->dev, "%s: unable to find core_clk rate\n", in cdns_ufs_set_hclkdiv()
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