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/linux/Documentation/devicetree/bindings/sound/
H A Ddai-params.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/dai-params.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 convert-channels:
21 convert-sample-format:
25 - s8
26 - s16_le
27 - s24_le
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/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dmain.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
14 driver Copyright(c) 2003 - 2004 Intel Corporation.
31 /* Lightweight function to convert a frequency (in Mhz) to a channel number. */
40 channel = (freq - 2407) / 5; in b43legacy_freq_to_channel_bg()
51 /* Lightweight function to convert a channel number to a frequency (in Mhz). */
73 int b43legacy_is_cck_rate(int rate) in b43legacy_is_cck_rate() argument
75 return (rate == B43legacy_CCK_RATE_1MB || in b43legacy_is_cck_rate()
76 rate == B43legacy_CCK_RATE_2MB || in b43legacy_is_cck_rate()
77 rate == B43legacy_CCK_RATE_5MB || in b43legacy_is_cck_rate()
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/linux/drivers/clk/hisilicon/
H A Dclk-hi6220-stub.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
71 regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq); in hi6220_acpu_get_freq()
81 regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq); in hi6220_acpu_set_freq()
89 mbox_send_message(stub_clk->mbox, &data); in hi6220_acpu_set_freq()
100 regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag); in hi6220_acpu_round_freq()
102 regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq); in hi6220_acpu_round_freq()
105 regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq); in hi6220_acpu_round_freq()
119 u32 rate = 0; in hi6220_stub_clk_recalc_rate() local
122 switch (stub_clk->id) { in hi6220_stub_clk_recalc_rate()
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/linux/drivers/tty/
H A Dtty_baudrate.c1 // SPDX-License-Identifier: GPL-2.0
15 * Routine which returns the baud rate of the tty
50 * Convert termios baud rate data into a speed. This should be called
53 * ->c_[io]speed directly as they are updated.
62 cbaud = termios->c_cflag & CBAUD; in tty_termios_baud_rate()
66 return termios->c_ospeed; in tty_termios_baud_rate()
80 * Convert termios baud rate data into a speed. This should be called
83 * ->c_[io]speed directly as they are updated.
90 unsigned int cbaud = (termios->c_cflag >> IBSHIFT) & CBAUD; in tty_termios_input_baud_rate()
97 return termios->c_ispeed; in tty_termios_input_baud_rate()
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/linux/include/drm/
H A Ddrm_audio_component.h1 // SPDX-License-Identifier: MIT
14 * struct drm_audio_component_ops - Ops implemented by DRM driver, called by hda driver
45 * @sync_audio_rate: set n/cts based on the sample rate
48 * sample rate, it will call this function to set n/cts
50 int (*sync_audio_rate)(struct device *, int port, int pipe, int rate);
68 * struct drm_audio_component_audio_ops - Ops implemented by hda driver, called by DRM driver
85 * @pin2port: Check and convert from pin node to port number
87 * Called by HDA driver to check and convert from the pin widget node
94 * Called at binding master component, for HDA codec-specific
101 * Called at unbinding master component, for HDA codec-specific
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
18 * period of 6.4ns. In order to convert the scale counter into
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
41 * value in order to quickly convert it into a nanosecond clock,
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
58 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
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/linux/arch/arm/mach-omap2/
H A Dvoltage.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/platform_data/voltage-omap.h>
32 * struct omap_vfsm_instance - per-voltage manager FSM register/bitfield
47 * struct voltagedomain - omap voltage domain global structure.
55 * @read: read-modify-write a VC/VP register
80 u32 rate; member
109 * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
110 * @slew_rate: PMIC slew rate (in uv/us)
114 * @cmd_reg_addr: command (on, on-LP, ret, off) configuration register address
115 * @i2c_high_speed: whether VC uses I2C high-speed mode to PMIC
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H A Dvc.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "prm-regbits-34xx.h"
20 #include "prm-regbits-44xx.h"
52 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
101 * omap_vc_config_channel - configure VC channel to PMIC mappings
106 * - i2c slave address (SA)
107 * - voltage configuration address (RAV)
108 * - command configuration address (RAC) and enable bit (RACEN)
109 * - command values for ON, ONLP, RET and OFF (CMD)
112 * non-default channel. Starting with OMAP4, there are more than 2
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/linux/sound/core/oss/
H A Dlinear.c1 // SPDX-License-Identifier: LGPL-2.0+
3 * Linear conversion Plug-In
5 * Abramo Bagnara <abramo@alsa-project.org>
33 memcpy(p + data->copy_ofs, src + data->src_ofs, data->copy_bytes); in do_convert()
34 if (data->cvt_endian) in do_convert()
36 tmp ^= data->flip; in do_convert()
37 memcpy(dst, p + data->dst_ofs, data->dst_bytes); in do_convert()
40 static void convert(struct snd_pcm_plugin *plugin, in convert() function
45 struct linear_priv *data = (struct linear_priv *)plugin->extra_data; in convert()
47 int nchannels = plugin->src_format.channels; in convert()
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H A Dmulaw.c1 // SPDX-License-Identifier: LGPL-2.0+
3 * Mu-Law conversion Plug-In Interface
5 * Uros Bizjak <uros@kss-loka.si>
15 #define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
17 #define NSEGS (8) /* Number of u-law segments. */
41 * linear2ulaw() - Convert a linear PCM value to u-law
44 * is biased by adding 33 which shifts the encoding range from (0 - 8158) to
45 * (33 - 8191). The result can be seen in the following encoding table:
48 * ------------------------ ---------------
61 * four bits wxyz. * The trailing bits (a - h) are ignored.
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/linux/drivers/clk/bcm/
H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
50 /* Convert a divider into the scaled divisor value it represents. */
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
61 return (u64)div->u.fixed; in scaled_div_min()
72 return (u64)div->u.fixed; in scaled_div_max()
74 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
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/linux/sound/soc/generic/
H A Dsimple-card-utils.c1 // SPDX-License-Identifier: GPL-2.0
3 // simple-card-utils.c
7 #include <dt-bindings/sound/audio-graph.h>
28 int val = -EINVAL; in simple_util_get_sample_fmt()
42 if (!strcmp(data->convert_sample_format, in simple_util_get_sample_fmt()
78 /* sampling rate convert */ in simple_util_parse_convert()
79 snprintf(prop, sizeof(prop), "%s%s", prefix, "convert-rate"); in simple_util_parse_convert()
80 of_property_read_u32(np, prop, &data->convert_rate); in simple_util_parse_convert()
83 snprintf(prop, sizeof(prop), "%s%s", prefix, "convert-channels"); in simple_util_parse_convert()
84 of_property_read_u32(np, prop, &data->convert_channels); in simple_util_parse_convert()
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/linux/sound/soc/sof/
H A Dipc4-pcm.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
11 #include "sof-audio.h"
12 #include "sof-priv.h"
14 #include "ipc4-priv.h"
15 #include "ipc4-topology.h"
16 #include "ipc4-fw-reg.h"
19 * struct sof_ipc4_timestamp_info - IPC4 timestamp info
23 * frames at host_copier sampling rate)
25 * frames at host_copier sampling rate)
29 * sampling rate.
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Drate.h34 /* phy rate in kbps [20Mhz] */
36 /* phy rate in kbps [40Mhz] */
38 /* phy rate in kbps [20Mhz] with SGI */
40 /* phy rate in kbps [40Mhz] with SGI */
42 /* phy ctl byte 3, code rate, modulation type, # of streams */
44 /* matching legacy ofdm rate in 500bkps */
52 #define MCS_TXS_MASK 0xc0 /* num tx streams - 1 bit mask */
53 #define MCS_TXS_SHIFT 6 /* num tx streams - 1 bit shift */
55 /* returns num tx streams - 1 */
75 #define BRCMS_RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */
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/linux/drivers/media/rc/img-ir/
H A Dimg-ir-hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright 2010-2014 Imagination Technologies Ltd.
12 #include <media/rc-core.h>
18 #define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */
19 #define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */
25 * struct img_ir_control - Decoder control settings
53 * struct img_ir_timing_range - range of timing values
65 * struct img_ir_symbol_timing - timing data for a symbol
75 * struct img_ir_free_timing - timing data for free time symbol
88 * struct img_ir_timings - Timing values.
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/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dhtb.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
12 u64 rate; member
16 u32 classid; /* 16-bit, except root. */
39 hash_for_each(htb->qos_tc2node, bkt, node, hnode) { in mlx5e_htb_enumerate_leaves()
40 if (node->qid == MLX5E_QOS_QID_INNER) in mlx5e_htb_enumerate_leaves()
42 err = callback(data, node->qid, node->hw_id); in mlx5e_htb_enumerate_leaves()
53 last = find_last_bit(htb->qos_used_qids, mlx5e_qos_max_leaf_nodes(htb->mdev)); in mlx5e_htb_cur_leaf_nodes()
54 return last == mlx5e_qos_max_leaf_nodes(htb->mdev) ? 0 : last + 1; in mlx5e_htb_cur_leaf_nodes()
59 int size = mlx5e_qos_max_leaf_nodes(htb->mdev); in mlx5e_htb_find_unused_qos_qid()
60 struct mlx5e_priv *priv = htb->priv; in mlx5e_htb_find_unused_qos_qid()
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/linux/sound/core/
H A Dpcm_misc.c1 // SPDX-License-Identifier: LGPL-2.0+
3 * PCM Interface - misc routines
14 #define SND_PCM_FORMAT_UNKNOWN (-1)
22 signed char le; /* 0 = big-endian, 1 = little-endian, -1 = others */
23 signed char signd; /* 0 = unsigned, 1 = signed, -1 = others */
37 .width = 8, .phys = 8, .le = -1, .signd = 1,
41 .width = 8, .phys = 8, .le = -1, .signd = 0,
93 .width = 32, .phys = 32, .le = 1, .signd = -1,
97 .width = 32, .phys = 32, .le = 0, .signd = -1,
101 .width = 64, .phys = 64, .le = 1, .signd = -1,
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/linux/net/sched/
H A Dsch_pie.c1 // SPDX-License-Identifier: GPL-2.0-only
37 u64 local_prob = vars->prob; in pie_drop_early()
41 if (vars->burst_time > 0) in pie_drop_early()
47 if ((vars->qdelay < params->target / 2) && in pie_drop_early()
48 (vars->prob < MAX_PROB / 5)) in pie_drop_early()
51 /* If we have fewer than 2 mtu-sized packets, disable pie_drop_early, in pie_drop_early()
60 if (params->bytemode && packet_size <= mtu) in pie_drop_early()
63 local_prob = vars->prob; in pie_drop_early()
66 vars->accu_prob = 0; in pie_drop_early()
68 vars->accu_prob += local_prob; in pie_drop_early()
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/linux/drivers/clk/rockchip/
H A Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
43 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
51 unsigned long rate = clk_hw_get_rate(hw); in rockchip_mmc_get_phase() local
57 if (!rate) in rockchip_mmc_get_phase()
60 if (mmc_clock->grf) in rockchip_mmc_get_phase()
61 regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value); in rockchip_mmc_get_phase()
63 raw_value = readl(mmc_clock->reg); in rockchip_mmc_get_phase()
65 raw_value >>= mmc_clock->shift; in rockchip_mmc_get_phase()
72 36 * (rate / 10000); in rockchip_mmc_get_phase()
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_txrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
11 /* Interrupt Throttling and Rate Limiting Goodies */
33 /* 0x40 is the enable bit for interrupt rate limiting, and must be set if
34 * the value of the rate limit is non-zero
41 * i40e_intrl_usec_to_reg - convert interrupt rate limit to register
42 * @intrl: interrupt rate limit to convert
44 * This function converts a decimal interrupt rate limit to the appropriate
45 * register format expected by the firmware when setting interrupt rate limit.
97 (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, (pf)->hw.caps) ? \
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/linux/drivers/clk/tegra/
H A Dclk-dfll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
17 * complex when the target CPU speed is above a particular rate. The
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
27 * performance-measurement code and any code that relies on the CPU
32 #include <linux/clk-provider.h>
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/linux/drivers/clk/ingenic/
H A Dcgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
11 #include <linux/clk-provider.h>
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
39 * caller must hold cgu->lock.
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
48 ^ info->clear_to_gate; in ingenic_cgu_gate_get()
52 * ingenic_cgu_gate_set() - set the value of clock gate register bit
55 * @val: non-zero to gate a clock, otherwise zero
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-pko.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
35 #include <asm/octeon/cvmx-pko.h>
36 #include <asm/octeon/cvmx-helper.h>
64 return -1; in __cvmx_pko_int()
85 config.s.tail = (queue == (num_queues - 1)); in __cvmx_pko_iport_config()
95 (CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - in __cvmx_pko_iport_config()
196 config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1; in cvmx_pko_initialize_global()
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
32 * check that the hardware can drive the required clock rate, in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid() local
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
39 if (rate != req_rate) { in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
63 clk_prepare_enable(hwdev->pxlclk); in malidp_crtc_atomic_enable()
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/linux/net/netfilter/
H A Dxt_limit.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* (C) 1999 Jérôme de Vivie <devivie@info.enserb.u-bordeaux.fr>
3 * (C) 1999 Hervé Eychenne <eychenne@info.enserb.u-bordeaux.fr>
4 * (C) 2006-2012 Patrick McHardy <kaber@trash.net>
23 MODULE_DESCRIPTION("Xtables: rate-limit match");
31 /* Rusty: This is my (non-mathematically-inclined) understanding of
32 this algorithm. The `average rate' in jiffies becomes your initial
34 `credit_cap'. The `peak rate' becomes the cost of passing the
45 credits per jiffy). We want to allow a rate as low as 1 per day
65 const struct xt_rateinfo *r = par->matchinfo; in limit_mt()
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