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/linux/Documentation/devicetree/bindings/sound/
H A Ddai-params.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/dai-params.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 convert-channels:
21 convert-sample-format:
25 - s8
26 - s16_le
27 - s24_le
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/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dmain.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
14 driver Copyright(c) 2003 - 2004 Intel Corporation.
31 /* Lightweight function to convert a frequency (in Mhz) to a channel number. */
40 channel = (freq - 2407) / 5; in b43legacy_freq_to_channel_bg()
51 /* Lightweight function to convert a channel number to a frequency (in Mhz). */
73 int b43legacy_is_cck_rate(int rate) in b43legacy_is_cck_rate() argument
75 return (rate == B43legacy_CCK_RATE_1MB || in b43legacy_is_cck_rate()
76 rate == B43legacy_CCK_RATE_2MB || in b43legacy_is_cck_rate()
77 rate == B43legacy_CCK_RATE_5MB || in b43legacy_is_cck_rate()
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/linux/drivers/net/wireless/intel/iwlwifi/fw/
H A Drs.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2021-2022 Intel Corporation
8 #include "iwl-drv.h"
9 #include "iwl-config.h"
96 int rate = rate_n_flags & RATE_LEGACY_RATE_MSK_V1; in iwl_legacy_rate_to_fw_idx() local
103 if (iwl_fw_rate_idx_to_plcp(idx) == rate) in iwl_legacy_rate_to_fw_idx()
104 return idx - offset; in iwl_legacy_rate_to_fw_idx()
115 /* convert rate */ in iwl_new_rate_from_v1()
142 /* the new rate have an additional bit to in iwl_new_rate_from_v1()
144 * bit for this purpose - as it was done in the old in iwl_new_rate_from_v1()
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/linux/drivers/clk/hisilicon/
H A Dclk-hi6220-stub.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
71 regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq); in hi6220_acpu_get_freq()
81 regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq); in hi6220_acpu_set_freq()
89 mbox_send_message(stub_clk->mbox, &data); in hi6220_acpu_set_freq()
100 regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag); in hi6220_acpu_round_freq()
102 regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq); in hi6220_acpu_round_freq()
105 regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq); in hi6220_acpu_round_freq()
119 u32 rate = 0; in hi6220_stub_clk_recalc_rate() local
122 switch (stub_clk->id) { in hi6220_stub_clk_recalc_rate()
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/linux/drivers/tty/
H A Dtty_baudrate.c1 // SPDX-License-Identifier: GPL-2.0
15 * Routine which returns the baud rate of the tty
50 * Convert termios baud rate data into a speed. This should be called
53 * ->c_[io]speed directly as they are updated.
62 cbaud = termios->c_cflag & CBAUD; in tty_termios_baud_rate()
66 return termios->c_ospeed; in tty_termios_baud_rate()
80 * Convert termios baud rate data into a speed. This should be called
83 * ->c_[io]speed directly as they are updated.
90 unsigned int cbaud = (termios->c_cflag >> IBSHIFT) & CBAUD; in tty_termios_input_baud_rate()
97 return termios->c_ispeed; in tty_termios_input_baud_rate()
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/linux/include/drm/
H A Ddrm_audio_component.h1 // SPDX-License-Identifier: MIT
14 * struct drm_audio_component_ops - Ops implemented by DRM driver, called by hda driver
45 * @sync_audio_rate: set n/cts based on the sample rate
48 * sample rate, it will call this function to set n/cts
50 int (*sync_audio_rate)(struct device *, int port, int pipe, int rate);
68 * struct drm_audio_component_audio_ops - Ops implemented by hda driver, called by DRM driver
85 * @pin2port: Check and convert from pin node to port number
87 * Called by HDA driver to check and convert from the pin widget node
94 * Called at binding master component, for HDA codec-specific
101 * Called at unbinding master component, for HDA codec-specific
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
18 * period of 6.4ns. In order to convert the scale counter into
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
41 * value in order to quickly convert it into a nanosecond clock,
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
58 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
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/linux/drivers/rtc/
H A Drtc-ac100.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTC Driver for X-Powers AC100
5 * Copyright (c) 2016 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk-provider.h>
62 * the year 1900. This macro is used to convert this offset to another one
65 * The year range is 1970 - 2069. This range is selected to match Allwinner's
70 #define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900)
80 #define AC100_RTC_32K_NAME "ac100-rtc-32k"
85 "ac100-cko1-rtc",
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/linux/arch/arm/mach-omap2/
H A Dvoltage.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/platform_data/voltage-omap.h>
32 * struct omap_vfsm_instance - per-voltage manager FSM register/bitfield
47 * struct voltagedomain - omap voltage domain global structure.
55 * @read: read-modify-write a VC/VP register
80 u32 rate; member
109 * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
110 * @slew_rate: PMIC slew rate (in uv/us)
114 * @cmd_reg_addr: command (on, on-LP, ret, off) configuration register address
115 * @i2c_high_speed: whether VC uses I2C high-speed mode to PMIC
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H A Dvc.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "prm-regbits-34xx.h"
20 #include "prm-regbits-44xx.h"
52 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
101 * omap_vc_config_channel - configure VC channel to PMIC mappings
106 * - i2c slave address (SA)
107 * - voltage configuration address (RAV)
108 * - command configuration address (RAC) and enable bit (RACEN)
109 * - command values for ON, ONLP, RET and OFF (CMD)
112 * non-default channel. Starting with OMAP4, there are more than 2
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/linux/sound/usb/
H A Dproc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 /* convert our full speed USB rate into sampling rate in Hz */
24 /* convert our high speed USB rate into sampling rate in Hz */
35 struct snd_usb_audio *chip = entry->private_data; in proc_audio_usbbus_read()
36 if (!atomic_read(&chip->shutdown)) in proc_audio_usbbus_read()
37 snd_iprintf(buffer, "%03d/%03d\n", chip->dev->bus->busnum, chip->dev->devnum); in proc_audio_usbbus_read()
42 struct snd_usb_audio *chip = entry->private_data; in proc_audio_usbid_read()
43 if (!atomic_read(&chip->shutdown)) in proc_audio_usbid_read()
45 USB_ID_VENDOR(chip->usb_id), in proc_audio_usbid_read()
46 USB_ID_PRODUCT(chip->usb_id)); in proc_audio_usbid_read()
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/linux/drivers/clk/bcm/
H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
27 /* Produces a mask of set bits covering a range of a 32-bit value */
30 return ((1 << width) - 1) << shift; in bitfield_mask()
49 /* Convert a divider into the scaled divisor value it represents. */
52 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
68 combined <<= div->u.s.frac_width; in scaled_div_build()
78 return (u64)div->u.fixed; in scaled_div_min()
89 return (u64)div->u.fixed; in scaled_div_max()
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/linux/sound/core/oss/
H A Dlinear.c2 * Linear conversion Plug-In
4 * Abramo Bagnara <abramo@alsa-project.org>
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 memcpy(p + data->copy_ofs, src + data->src_ofs, data->copy_bytes); in do_convert()
49 if (data->cvt_endian) in do_convert()
51 tmp ^= data->flip; in do_convert()
52 memcpy(dst, p + data->dst_ofs, data->dst_bytes); in do_convert()
55 static void convert(struct snd_pcm_plugin *plugin, in convert() function
60 struct linear_priv *data = (struct linear_priv *)plugin->extra_data; in convert()
62 int nchannels = plugin->src_format.channels; in convert()
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H A Dmulaw.c2 * Mu-Law conversion Plug-In Interface
4 * Uros Bizjak <uros@kss-loka.si>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
31 #define NSEGS (8) /* Number of u-law segments. */
55 * linear2ulaw() - Convert a linear PCM value to u-law
58 * is biased by adding 33 which shifts the encoding range from (0 - 8158) to
59 * (33 - 8191). The result can be seen in the following encoding table:
62 * ------------------------ ---------------
75 * four bits wxyz. * The trailing bits (a - h) are ignored.
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Drate.h34 /* phy rate in kbps [20Mhz] */
36 /* phy rate in kbps [40Mhz] */
38 /* phy rate in kbps [20Mhz] with SGI */
40 /* phy rate in kbps [40Mhz] with SGI */
42 /* phy ctl byte 3, code rate, modulation type, # of streams */
44 /* matching legacy ofdm rate in 500bkps */
52 #define MCS_TXS_MASK 0xc0 /* num tx streams - 1 bit mask */
53 #define MCS_TXS_SHIFT 6 /* num tx streams - 1 bit shift */
55 /* returns num tx streams - 1 */
75 #define BRCMS_RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */
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/linux/drivers/media/rc/img-ir/
H A Dimg-ir-hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright 2010-2014 Imagination Technologies Ltd.
12 #include <media/rc-core.h>
18 #define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */
19 #define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */
25 * struct img_ir_control - Decoder control settings
53 * struct img_ir_timing_range - range of timing values
65 * struct img_ir_symbol_timing - timing data for a symbol
75 * struct img_ir_free_timing - timing data for free time symbol
88 * struct img_ir_timings - Timing values.
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H A Dimg-ir-hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2014 Imagination Technologies Ltd.
7 * This ties into the input subsystem using the RC-core. Protocol support is
18 #include <media/rc-core.h>
19 #include "img-ir.h"
68 if (range->max < range->min) in img_ir_timing_preprocess()
69 range->max = range->min; in img_ir_timing_preprocess()
71 /* multiply by unit and convert to microseconds */ in img_ir_timing_preprocess()
72 range->min = (range->min*unit)/1000; in img_ir_timing_preprocess()
73 range->max = (range->max*unit + 999)/1000; /* round up */ in img_ir_timing_preprocess()
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/linux/net/sched/
H A Dsch_pie.c1 // SPDX-License-Identifier: GPL-2.0-only
37 u64 local_prob = vars->prob; in pie_drop_early()
41 if (vars->burst_time > 0) in pie_drop_early()
47 if ((vars->qdelay < params->target / 2) && in pie_drop_early()
48 (vars->prob < MAX_PROB / 5)) in pie_drop_early()
51 /* If we have fewer than 2 mtu-sized packets, disable pie_drop_early, in pie_drop_early()
60 if (params->bytemode && packet_size <= mtu) in pie_drop_early()
63 local_prob = vars->prob; in pie_drop_early()
66 vars->accu_prob = 0; in pie_drop_early()
68 vars->accu_prob += local_prob; in pie_drop_early()
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/linux/drivers/clk/rockchip/
H A Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
40 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
48 unsigned long rate = clk_hw_get_rate(hw); in rockchip_mmc_get_phase() local
54 if (!rate) in rockchip_mmc_get_phase()
57 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
64 36 * (rate / 10000); in rockchip_mmc_get_phase()
77 unsigned long rate = clk_hw_get_rate(hw); in rockchip_mmc_set_phase() local
86 * the clock rate from its parent, namely the output clock in rockchip_mmc_set_phase()
95 if (!rate) { in rockchip_mmc_set_phase()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dhtb.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
12 u64 rate; member
16 u32 classid; /* 16-bit, except root. */
39 hash_for_each(htb->qos_tc2node, bkt, node, hnode) { in mlx5e_htb_enumerate_leaves()
40 if (node->qid == MLX5E_QOS_QID_INNER) in mlx5e_htb_enumerate_leaves()
42 err = callback(data, node->qid, node->hw_id); in mlx5e_htb_enumerate_leaves()
53 last = find_last_bit(htb->qos_used_qids, mlx5e_qos_max_leaf_nodes(htb->mdev)); in mlx5e_htb_cur_leaf_nodes()
54 return last == mlx5e_qos_max_leaf_nodes(htb->mdev) ? 0 : last + 1; in mlx5e_htb_cur_leaf_nodes()
59 int size = mlx5e_qos_max_leaf_nodes(htb->mdev); in mlx5e_htb_find_unused_qos_qid()
60 struct mlx5e_priv *priv = htb->priv; in mlx5e_htb_find_unused_qos_qid()
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/linux/sound/core/
H A Dpcm_misc.c2 * PCM Interface - misc routines
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define SND_PCM_FORMAT_UNKNOWN (-1)
37 signed char le; /* 0 = big-endian, 1 = little-endian, -1 = others */
38 signed char signd; /* 0 = unsigned, 1 = signed, -1 = others */
52 .width = 8, .phys = 8, .le = -1, .signd = 1,
56 .width = 8, .phys = 8, .le = -1, .signd = 0,
108 .width = 32, .phys = 32, .le = 1, .signd = -1,
112 .width = 32, .phys = 32, .le = 0, .signd = -1,
116 .width = 64, .phys = 64, .le = 1, .signd = -1,
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/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
38 …(amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_…
43 …amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.ato…
47 bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
89 if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, in bios_cmd_table_para_revision()
125 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v3; in init_dig_encoder_control()
128 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v4; in init_dig_encoder_control()
132 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v5; in init_dig_encoder_control()
153 struct cmd_tbl *cmd_tbl = &bp->cmd_tbl; in init_encoder_control_dig_v1()
156 cmd_tbl->encoder_control_dig1 = encoder_control_dig1_v1; in init_encoder_control_dig_v1()
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/linux/drivers/clk/qcom/
H A Dclk-rpmh.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
12 #include <soc/qcom/cmd-db.h>
16 #include <dt-bindings/clock/qcom,rpmh.h>
22 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
23 * @unit: divisor used to convert Hz value to an RPMh msg
24 * @width: multiplier used to convert Hz value to an RPMh msg
36 * struct clk_rpmh - individual rpmh clock data structure
37 * @hw: handle between common and hardware-specific interfaces
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_txrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
10 /* Interrupt Throttling and Rate Limiting Goodies */
32 /* 0x40 is the enable bit for interrupt rate limiting, and must be set if
33 * the value of the rate limit is non-zero
40 * i40e_intrl_usec_to_reg - convert interrupt rate limit to register
41 * @intrl: interrupt rate limit to convert
43 * This function converts a decimal interrupt rate limit to the appropriate
44 * register format expected by the firmware when setting interrupt rate limit.
96 (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, (pf)->hw.caps) ? \
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/linux/drivers/clk/tegra/
H A Dclk-dfll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
17 * complex when the target CPU speed is above a particular rate. The
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
27 * performance-measurement code and any code that relies on the CPU
32 #include <linux/clk-provider.h>
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