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/linux/drivers/greybus/
H A Dcontrol.c3 * Greybus CPort control protocol.
14 /* Highest control-protocol version supported */
18 static int gb_control_get_version(struct gb_control *control) in gb_control_get_version() argument
20 struct gb_interface *intf = control->connection->intf; in gb_control_get_version()
28 ret = gb_operation_sync(control->connection, in gb_control_get_version()
34 "failed to get control-protocol version: %d\n", in gb_control_get_version()
41 "unsupported major control-protocol version (%u > %u)\n", in gb_control_get_version()
46 control->protocol_major = response.major; in gb_control_get_version()
47 control->protocol_minor = response.minor; in gb_control_get_version()
55 static int gb_control_get_bundle_version(struct gb_control *control, in gb_control_get_bundle_version() argument
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h13 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
14 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
19 #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
20 #define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
21 #define PA_PCICD (PA_BCR+0x0010) /* PCI Connector detect control */
22 #define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
23 #define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
24 #define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
25 #define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
26 #define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
[all …]
H A Dr2d.h16 #define PA_IRLMON 0xa4000002 /* Interrupt Status control */
17 #define PA_CFCTL 0xa4000004 /* CF Timing control */
18 #define PA_CFPOW 0xa4000006 /* CF Power control */
19 #define PA_DISPCTL 0xa4000008 /* Display Timing control */
20 #define PA_SDMPOW 0xa400000a /* SD Power control */
21 #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
22 #define PA_PCICD 0xa400000e /* PCI Extension detect control */
23 #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
25 #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */
26 #define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ras_eeprom.c128 * add to control->i2c_address, and then tell I2C layer to read
172 struct amdgpu_ras_eeprom_control *control) in __get_eeprom_i2c_addr() argument
177 if (!control) in __get_eeprom_i2c_addr()
190 control->i2c_address = ((u32) i2c_addr) << 16; in __get_eeprom_i2c_addr()
199 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
203 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
205 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
208 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
213 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
215 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
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H A Dsmu_v11_0_i2c.c47 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en) in smu_v11_0_i2c_set_clock_gating() argument
49 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_set_clock_gating()
76 static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable) in smu_v11_0_i2c_enable() argument
78 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_enable()
102 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control) in smu_v11_0_i2c_clear_status() argument
104 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_clear_status()
113 static void smu_v11_0_i2c_configure(struct i2c_adapter *control) in smu_v11_0_i2c_configure() argument
115 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_configure()
135 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control) in smu_v11_0_i2c_set_clock() argument
137 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_set_clock()
[all …]
/linux/include/sound/
H A Dseq_midi_emul.h35 unsigned char control[128]; /* Current value of all controls */ member
73 void (*control)(void *private_data, int type, struct snd_midi_channel *chan); member
94 #define gm_bank_select control[0]
95 #define gm_modulation control[1]
96 #define gm_breath control[2]
97 #define gm_foot_pedal control[4]
98 #define gm_portamento_time control[5]
99 #define gm_data_entry control[6]
100 #define gm_volume control[7]
101 #define gm_balance control[8]
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H A Dcs4231-regs.h21 #define CS4231_LEFT_INPUT 0x00 /* left input control */
22 #define CS4231_RIGHT_INPUT 0x01 /* right input control */
23 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
24 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
25 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
26 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
27 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
28 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
30 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
31 #define CS4231_PIN_CTRL 0x0a /* pin control */
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/linux/include/linux/mfd/
H A Dmotorola-cpcap.h47 #define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */
48 #define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */
54 #define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */
55 #define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */
60 #define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */
66 #define CPCAP_REG_SCC 0x0400 /* System Clock Control */
80 #define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */
81 #define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */
82 #define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */
83 #define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */
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/linux/drivers/tty/vt/
H A Ddefkeymap.map7 # altgr control keycode 83 = Boot
8 # altgr control keycode 111 = Boot
20 control keycode 3 = nul
21 shift control keycode 3 = nul
24 control keycode 4 = Escape
27 control keycode 5 = Control_backslash
30 control keycode 6 = Control_bracketright
33 control keycode 7 = Control_asciicircum
36 control keycode 8 = Control_underscore
39 control keycode 9 = Delete
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.h36 #define B43_LPPHY_TSSI_CTL B43_PHY_CCK(0x28) /* TSSI Control */
80 #define B43_LPPHY_FINEDIGIGAIN_CTL B43_PHY_CCK(0x67) /* FineDigiGain Control */
106 #define B43_LPPHY_CRSGAIN_CTL B43_PHY_OFDM(0x10) /* crsgain Control */
117 #define B43_LPPHY_LTRN_CTL B43_PHY_OFDM(0x1B) /* LTRN Control */
123 #define B43_LPPHY_OFDMSYNCTIMER_CTL B43_PHY_OFDM(0x21) /* ofdmSyncTimer Control */
141 #define B43_LPPHY_PHASE_SHIFT_CTL B43_PHY_OFDM(0x33) /* phase shift Control */
143 #define B43_LPPHY_OFDM_SYNC_CTL B43_PHY_OFDM(0x35) /* ofdm sync Control */
144 #define B43_LPPHY_AFE_ADC_CTL_0 B43_PHY_OFDM(0x36) /* Afe ADC Control 0 */
145 #define B43_LPPHY_AFE_ADC_CTL_1 B43_PHY_OFDM(0x37) /* Afe ADC Control 1 */
146 #define B43_LPPHY_AFE_ADC_CTL_2 B43_PHY_OFDM(0x38) /* Afe ADC Control 2 */
[all …]
/linux/include/linux/greybus/
H A Dcontrol.h3 * Greybus CPort control protocol
33 int gb_control_enable(struct gb_control *control);
34 void gb_control_disable(struct gb_control *control);
35 int gb_control_suspend(struct gb_control *control);
36 int gb_control_resume(struct gb_control *control);
37 int gb_control_add(struct gb_control *control);
38 void gb_control_del(struct gb_control *control);
39 struct gb_control *gb_control_get(struct gb_control *control);
40 void gb_control_put(struct gb_control *control);
42 int gb_control_get_bundle_versions(struct gb_control *control);
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dextended-controls.rst13 The control mechanism as originally designed was meant to be used for
19 implementing this extended control mechanism: the MPEG standard is quite
27 Unfortunately, the original control API lacked some features needed for
29 named) extended control API.
32 Extended Control API, nowadays there are also other classes of Extended
38 The Extended Control API
48 control). This is needed since it is often required to atomically change
53 contains a pointer to the control array, a count of the number of
54 controls in that array and a control class. Control classes are used to
55 group similar controls into a single class. For example, control class
[all …]
/linux/drivers/media/i2c/
H A Dadv7183_regs.h11 #define ADV7183_IN_CTRL 0x00 /* Input control */
13 #define ADV7183_OUT_CTRL 0x03 /* Output control */
14 #define ADV7183_EXT_OUT_CTRL 0x04 /* Extended output control */
21 #define ADV7183_ADI_CTRL 0x0E /* ADI control */
27 #define ADV7183_ANAL_CLAMP_CTRL 0x14 /* Analog clamp control */
28 #define ADV7183_DIGI_CLAMP_CTRL_1 0x15 /* Digital clamp control 1 */
29 #define ADV7183_SHAP_FILT_CTRL 0x17 /* Shaping filter control */
30 #define ADV7183_SHAP_FILT_CTRL_2 0x18 /* Shaping filter control 2 */
31 #define ADV7183_COMB_FILT_CTRL 0x19 /* Comb filter control */
32 #define ADV7183_ADI_CTRL_2 0x1D /* ADI control 2 */
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/linux/Documentation/driver-api/media/
H A Dv4l2-controls.rst9 The V4L2 control API seems simple enough, but quickly becomes very hard to
15 1) How do I add a control?
16 2) How do I set the control's value? (i.e. s_ctrl)
20 3) How do I get the control's value? (i.e. g_volatile_ctrl)
21 4) How do I validate the user's proposed control value? (i.e. try_ctrl)
25 The control framework was created in order to implement all the rules of the
29 Note that the control framework relies on the presence of a struct
39 The :c:type:`v4l2_ctrl` object describes the control properties and keeps
40 track of the control's value (both the current value and the proposed new
93 1.3) Hook the control handler into the driver:
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/linux/drivers/s390/char/
H A Ddefkeymap.map135 control keycode 74 = F22
136 control keycode 75 = F23
137 control keycode 76 = F24
138 control keycode 107 = Control_z # PA3
139 control keycode 108 = Control_c # PA1
140 control keycode 109 = KeyboardSignal # Clear
141 control keycode 110 = Control_d # PA2
142 control keycode 122 = F10
143 control keycode 123 = F11 # F11
144 control keycode 124 = Last_Console # F12
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmicrel-ksz90x1.txt14 All skew control options are specified in picoseconds. The minimum
48 - rxc-skew-ps : Skew control of RXC pad
49 - rxdv-skew-ps : Skew control of RX CTL pad
50 - txc-skew-ps : Skew control of TXC pad
51 - txen-skew-ps : Skew control of TX CTL pad
52 - rxd0-skew-ps : Skew control of RX data 0 pad
53 - rxd1-skew-ps : Skew control of RX data 1 pad
54 - rxd2-skew-ps : Skew control of RX data 2 pad
55 - rxd3-skew-ps : Skew control of RX data 3 pad
56 - txd0-skew-ps : Skew control of TX data 0 pad
[all …]
/linux/arch/powerpc/include/asm/
H A Dreg_fsl_emb.h44 #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
45 #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
46 #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
47 #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
48 #define PMRN_PMLCA4 0x094 /* PM Local Control A4 */
49 #define PMRN_PMLCA5 0x095 /* PM Local Control A5 */
63 #define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
64 #define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
65 #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
66 #define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
[all …]
/linux/sound/soc/sof/
H A Dcontrol.c27 if (tplg_ops && tplg_ops->control && tplg_ops->control->volume_get) in snd_sof_volume_get()
28 return tplg_ops->control->volume_get(scontrol, ucontrol); in snd_sof_volume_get()
42 if (tplg_ops && tplg_ops->control && tplg_ops->control->volume_put) in snd_sof_volume_put()
43 return tplg_ops->control->volume_put(scontrol, ucontrol); in snd_sof_volume_put()
79 if (tplg_ops && tplg_ops->control && tplg_ops->control->switch_get) in snd_sof_switch_get()
80 return tplg_ops->control->switch_get(scontrol, ucontrol); in snd_sof_switch_get()
94 if (tplg_ops && tplg_ops->control && tplg_ops->control->switch_put) in snd_sof_switch_put()
95 return tplg_ops->control->switch_put(scontrol, ucontrol); in snd_sof_switch_put()
109 if (tplg_ops && tplg_ops->control && tplg_ops->control->enum_get) in snd_sof_enum_get()
110 return tplg_ops->control->enum_get(scontrol, ucontrol); in snd_sof_enum_get()
[all …]
/linux/sound/pci/emu10k1/
H A Dp17v.h50 #define ADC_IFC_CTRL 0x0000000b /*ADC Interface Control */
51 #define ADC_MASTER 0x0000000c /*ADC Master Mode Control */
52 #define ADC_POWER 0x0000000d /*ADC PowerDown Control */
55 #define ADC_ALC_CTRL1 0x00000010 /*ADC ALC Control 1 */
56 #define ADC_ALC_CTRL2 0x00000011 /*ADC ALC Control 2 */
57 #define ADC_ALC_CTRL3 0x00000012 /*ADC ALC Control 3 */
58 #define ADC_NOISE_CTRL 0x00000013 /*ADC Noise Gate Control */
59 #define ADC_LIMIT_CTRL 0x00000014 /*ADC Limiter Control */
85 #define P17V_CAPTURE_VOL_H 0x4c /* P17v capture volume control */
86 #define P17V_CAPTURE_VOL_L 0x4d /* P17v capture volume control */
[all …]
/linux/include/linux/fsl/
H A Dguts.h32 * Control Register
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
53 * Multiplex Control
56 * multiplex control 2
58 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
60 u32 devdisr; /* 0x.0070 - Device Disable Control */
63 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
65 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
69 * Control Register
82 * Control Register
[all …]
/linux/sound/soc/codecs/
H A Dssm2602.h49 /*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/
50 #define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control …
54 /*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/
55 #define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control …
59 /*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/
60 #define LOUT1V_LHP_VOL 0x07F /* Left Channel Headphone volume control …
64 /*Right DAC Volume Control (SSM2602_REG_RIGHT_DAC_VOL)*/
65 #define ROUT1V_RHP_VOL 0x07F /* Right Channel Headphone volume control …
69 /*Analogue Audio Path Control (SSM2602_REG_ANALOGUE_PATH)*/
70 … APANA_ENABLE_MIC_BOOST 0x001 /* Primary Microphone Amplifier gain booster control */
[all …]
H A Dcs53l30.h19 #define CS53L30_PWRCTL 0x06 /* Power Control. */
20 #define CS53L30_MCLKCTL 0x07 /* MCLK Control. */
21 #define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */
22 #define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */
23 #define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */
24 #define CS53L30_ASP_CTL1 0x0D /* ASP1 Control. */
25 #define CS53L30_ASP_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */
26 #define CS53L30_ASP_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */
27 #define CS53L30_ASP_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */
28 #define CS53L30_ASP_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */
[all …]
/linux/drivers/media/usb/pvrusb2/
H A Dpvrusb2-ctrl.h19 /* Set the given control. */
22 /* Set/clear specific bits of the given control. */
25 /* Get the current value of the given control. */
28 /* Retrieve control's type */
31 /* Retrieve control's maximum value (int type) */
34 /* Retrieve control's minimum value (int type) */
37 /* Retrieve control's default value (any type) */
40 /* Retrieve control's enumeration count (enum only) */
43 /* Retrieve control's valid mask bits (bit mask only) */
46 /* Retrieve the control's name */
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_mac.h70 /* Transmit Control Descriptor */
75 u32 ctl3; /* DMA control 3 */
77 u32 ctl5; /* DMA control 5 */
79 u32 ctl7; /* DMA control 7 */
81 u32 ctl9; /* DMA control 9 */
82 u32 ctl10; /* DMA control 10 */
83 u32 ctl11; /* DMA control 11 */
84 u32 ctl12; /* DMA control 12 */
85 u32 ctl13; /* DMA control 13 */
86 u32 ctl14; /* DMA control 14 */
[all …]
/linux/drivers/macintosh/
H A Dwindfarm_pm121.c3 * Windfarm PowerMac thermal control. iMac G5 iSight
13 * The algorithm used is the PID control algorithm, used the same way
21 * controls with a tiny difference. The control-ids of hard-drive-fan
31 * OD Fan control correction.
41 * HD Fan control correction.
51 * CPU Fan control correction.
64 * control value. The correction is computed in the following way :
68 * ref_value is the value of the reference control. If new_min is
74 * control : cpu-fan
80 * control : optical-drive-fan
[all …]

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