Lines Matching full:control
19 #define CS53L30_PWRCTL 0x06 /* Power Control. */
20 #define CS53L30_MCLKCTL 0x07 /* MCLK Control. */
21 #define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */
22 #define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */
23 #define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */
24 #define CS53L30_ASP_CTL1 0x0D /* ASP1 Control. */
25 #define CS53L30_ASP_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */
26 #define CS53L30_ASP_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */
27 #define CS53L30_ASP_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */
28 #define CS53L30_ASP_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */
35 #define CS53L30_ASP_CTL2 0x18 /* ASP2 Control. */
36 #define CS53L30_SFT_RAMP 0x1A /* Soft Ramp Control. */
37 #define CS53L30_LRCK_CTL1 0x1B /* LRCK Control 1. */
38 #define CS53L30_LRCK_CTL2 0x1C /* LRCK Control 2. */
39 #define CS53L30_MUTEP_CTL1 0x1F /* Mute Pin Control 1. */
40 #define CS53L30_MUTEP_CTL2 0x20 /* Mute Pin Control 2. */
41 #define CS53L30_INBIAS_CTL1 0x21 /* Input Bias Control 1. */
42 #define CS53L30_INBIAS_CTL2 0x22 /* Input Bias Control 2. */
43 #define CS53L30_DMIC1_STR_CTL 0x23 /* DMIC1 Stereo Control. */
44 #define CS53L30_DMIC2_STR_CTL 0x24 /* DMIC2 Stereo Control. */
45 #define CS53L30_ADCDMIC1_CTL1 0x25 /* ADC1/DMIC1 Control 1. */
46 #define CS53L30_ADCDMIC1_CTL2 0x26 /* ADC1/DMIC1 Control 2. */
47 #define CS53L30_ADC1_CTL3 0x27 /* ADC1 Control 3. */
48 #define CS53L30_ADC1_NG_CTL 0x28 /* ADC1 Noise Gate Control. */
49 #define CS53L30_ADC1A_AFE_CTL 0x29 /* ADC1A AFE Control. */
50 #define CS53L30_ADC1B_AFE_CTL 0x2A /* ADC1B AFE Control. */
53 #define CS53L30_ADCDMIC2_CTL1 0x2D /* ADC2/DMIC2 Control 1. */
54 #define CS53L30_ADCDMIC2_CTL2 0x2E /* ADC2/DMIC2 Control 2. */
55 #define CS53L30_ADC2_CTL3 0x2F /* ADC2 Control 3. */
56 #define CS53L30_ADC2_NG_CTL 0x30 /* ADC2 Noise Gate Control. */
57 #define CS53L30_ADC2A_AFE_CTL 0x31 /* ADC2A AFE Control. */
58 #define CS53L30_ADC2B_AFE_CTL 0x32 /* ADC2B AFE Control. */
83 /* R6 (0x06) CS53L30_PWRCTL - Power Control */
99 /* R7 (0x07) CS53L30_MCLKCTL - MCLK Control */
121 /* R8 (0x08) CS53L30_INT_SR_CTL - Internal Sample Rate Control */
132 /* R10 (0x0A) CS53L30_MICBIAS_CTL - Mic Bias Control */
158 /* R12 (0x0C) CS53L30_ASPCFG_CTL - ASP Configuration Control */
172 /* R13/R24 (0x0D/0x18) CS53L30_ASP_CTL1 & CS53L30_ASP_CTL2 - ASP Control 1~2 */
192 /* R14 (0x0E) ~ R17 (0x11) CS53L30_ASP_TDMTX_CTLx - ASP TDM TX Control 1~4 */
207 /* R26 (0x1A) CS53L30_SFT_RAMP - Soft Ramp Control */
214 /* R28 (0x1C) CS53L30_LRCK_CTL2 - LRCK Control 2 */
225 /* R31 (0x1F) CS53L30_MUTEP_CTL1 - MUTE Pin Control 1 */
255 /* R32 (0x20) CS53L30_MUTEP_CTL2 - MUTE Pin Control 2 */
287 /* R33 (0x21) CS53L30_INBIAS_CTL1 - Input Bias Control 1 */
316 /* R34 (0x22) CS53L30_INBIAS_CTL2 - Input Bias Control 2 */
345 /* R35 (0x23) & R36 (0x24) CS53L30_DMICx_STR_CTL - DMIC1 & DMIC2 Stereo Control */
354 /* R37/R45 (0x25/0x2D) CS53L30_ADCDMICx_CTL1 - ADC1/DMIC1 & ADC2/DMIC2 Control 1 */
374 /* R38/R46 (0x26/0x2E) CS53L30_ADCDMICx_CTL2 - ADC1/DMIC1 & ADC2/DMIC2 Control 2 */
393 /* R39/R47 (0x27/0x2F) CS53L30_ADCx_CTL3 - ADC1/ADC2 Control 3 */
410 /* R40/R48 (0x28/0x30) CS53L30_ADCx_NG_CTL - ADC1/ADC2 Noise Gate Control */
429 /* R41/R42/R49/R50 (0x29/0x2A/0x31/0x32) CS53L30_ADCxy_AFE_CTL - ADC1A/1B/2A/2B AFE Control */