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/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00config.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
24 struct rt2x00intf_conf conf; in rt2x00lib_config_intf() local
27 conf.type = type; in rt2x00lib_config_intf()
31 conf.sync = TSF_SYNC_ADHOC; in rt2x00lib_config_intf()
35 conf.sync = TSF_SYNC_AP_NONE; in rt2x00lib_config_intf()
38 conf.sync = TSF_SYNC_INFRA; in rt2x00lib_config_intf()
41 conf.sync = TSF_SYNC_NONE; in rt2x00lib_config_intf()
51 memset(conf.mac, 0, sizeof(conf.mac)); in rt2x00lib_config_intf()
53 memcpy(conf.mac, mac, ETH_ALEN); in rt2x00lib_config_intf()
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/linux/drivers/isdn/mISDN/
H A Ddsp_cmx.c20 * There are 3 different solutions: -1 = software, 0 = hardware-crossconnect
21 * 1-n = hardware-conference. The n will give the conference number.
39 * - Crossconnecting or even conference, if more than two members are together.
40 * - Force mixing of transmit data with other crossconnect/conference members.
41 * - Echo generation to benchmark the delay of audio processing.
42 * - Use hardware to minimize cpu load, disable FIFO load and minimize delay.
43 * - Dejittering and clock generation.
48 * RX-Buffer
51 * ----------------+-------------+-------------------
53 * The rx-buffer is a ring buffer used to store the received data for each
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cn9k.c1 // SPDX-License-Identifier: GPL-2.0
19 struct device *dev = &oct->pdev->dev; in cn93_vf_dump_q_regs()
21 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
50 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
80 /* Reset Hardware Tx queue */
85 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cn93_vf_reset_iq()
87 /* Disable the Tx/Instruction Ring */ in cn93_vf_reset_iq()
121 /* Reset all hardware Tx/Rx queues */
124 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cn93()
127 dev_dbg(&pdev->dev, "Reset OCTEP_CN93 VF IO Queues\n"); in octep_vf_reset_io_queues_cn93()
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H A Doctep_vf_cnxk.c1 // SPDX-License-Identifier: GPL-2.0
19 struct device *dev = &oct->pdev->dev; in cnxk_vf_dump_q_regs()
21 dev_info(dev, "IQ-%d register dump\n", qno); in cnxk_vf_dump_q_regs()
50 dev_info(dev, "OQ-%d register dump\n", qno); in cnxk_vf_dump_q_regs()
83 /* Reset Hardware Tx queue */
88 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cnxk_vf_reset_iq()
90 /* Disable the Tx/Instruction Ring */ in cnxk_vf_reset_iq()
123 /* Reset all hardware Tx/Rx queues */
126 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cnxk()
129 dev_dbg(&pdev->dev, "Reset OCTEP_CNXK VF IO Queues\n"); in octep_vf_reset_io_queues_cnxk()
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H A Doctep_vf_tx.c1 // SPDX-License-Identifier: GPL-2.0
16 /* Reset various index of Tx queue data structure. */
19 iq->fill_cnt = 0; in octep_vf_iq_reset_indices()
20 iq->host_write_index = 0; in octep_vf_iq_reset_indices()
21 iq->octep_vf_read_index = 0; in octep_vf_iq_reset_indices()
22 iq->flush_index = 0; in octep_vf_iq_reset_indices()
23 iq->pkts_processed = 0; in octep_vf_iq_reset_indices()
24 iq->pkt_in_done = 0; in octep_vf_iq_reset_indices()
28 * octep_vf_iq_process_completions() - Process Tx queue completions.
30 * @iq: Octeon Tx queue data structure.
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/linux/net/mac80211/
H A Dwpa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2002-2004, Instant802 Networks, Inc.
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 * Copyright (C) 2020-2023 Intel Corporation
30 ieee80211_tx_h_michael_mic_add(struct ieee80211_tx_data *tx) in ieee80211_tx_h_michael_mic_add() argument
36 struct sk_buff *skb = tx->skb; in ieee80211_tx_h_michael_mic_add()
40 hdr = (struct ieee80211_hdr *)skb->data; in ieee80211_tx_h_michael_mic_add()
41 if (!tx->key || tx->key->conf.cipher != WLAN_CIPHER_SUITE_TKIP || in ieee80211_tx_h_michael_mic_add()
42 skb->len < 24 || !ieee80211_is_data_present(hdr->frame_control)) in ieee80211_tx_h_michael_mic_add()
45 hdrlen = ieee80211_hdrlen(hdr->frame_control); in ieee80211_tx_h_michael_mic_add()
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H A Dwep.c1 // SPDX-License-Identifier: GPL-2.0-only
29 get_random_bytes(&local->wep_iv, IEEE80211_WEP_IV_LEN); in ieee80211_wep_init()
51 local->wep_iv++; in ieee80211_wep_get_iv()
52 if (ieee80211_wep_weak_iv(local->wep_iv, keylen)) in ieee80211_wep_get_iv()
53 local->wep_iv += 0x0100; in ieee80211_wep_get_iv()
58 *iv++ = (local->wep_iv >> 16) & 0xff; in ieee80211_wep_get_iv()
59 *iv++ = (local->wep_iv >> 8) & 0xff; in ieee80211_wep_get_iv()
60 *iv++ = local->wep_iv & 0xff; in ieee80211_wep_get_iv()
69 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; in ieee80211_wep_add_iv()
74 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PROTECTED); in ieee80211_wep_add_iv()
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
42 phy-mode = "rgmii-id";
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/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_tx.c1 // SPDX-License-Identifier: GPL-2.0
15 /* Reset various index of Tx queue data structure. */
18 iq->fill_cnt = 0; in octep_iq_reset_indices()
19 iq->host_write_index = 0; in octep_iq_reset_indices()
20 iq->octep_read_index = 0; in octep_iq_reset_indices()
21 iq->flush_index = 0; in octep_iq_reset_indices()
22 iq->pkts_processed = 0; in octep_iq_reset_indices()
23 iq->pkt_in_done = 0; in octep_iq_reset_indices()
27 * octep_iq_process_completions() - Process Tx queue completions.
29 * @iq: Octeon Tx queue data structure.
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H A Doctep_cn9k_pf.c1 // SPDX-License-Identifier: GPL-2.0
19 /* Names of Hardware non-queue generic interrupts */
42 struct device *dev = &oct->pdev->dev; in cn93_dump_regs()
44 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_dump_regs()
73 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_dump_regs()
106 /* Reset Hardware Tx queue */
109 struct octep_config *conf = oct->conf; in cn93_reset_iq() local
112 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); in cn93_reset_iq()
115 q_no += conf->pf_ring_cfg.srn; in cn93_reset_iq()
117 /* Disable the Tx/Instruction Ring */ in cn93_reset_iq()
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H A Doctep_cnxk_pf.c1 // SPDX-License-Identifier: GPL-2.0
20 /* Names of Hardware non-queue generic interrupts */
62 struct device *dev = &oct->pdev->dev; in cnxk_dump_regs()
64 dev_info(dev, "IQ-%d register dump\n", qno); in cnxk_dump_regs()
93 dev_info(dev, "OQ-%d register dump\n", qno); in cnxk_dump_regs()
126 /* Reset Hardware Tx queue */
129 struct octep_config *conf = oct->conf; in cnxk_reset_iq() local
132 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); in cnxk_reset_iq()
135 q_no += conf->pf_ring_cfg.srn; in cnxk_reset_iq()
137 /* Disable the Tx/Instruction Ring */ in cnxk_reset_iq()
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H A Doctep_main.c1 // SPDX-License-Identifier: GPL-2.0
42 * octep_alloc_ioq_vectors() - Allocate Tx/Rx Queue interrupt info.
46 * Allocate resources to hold per Tx/Rx queue interrupt info.
48 * is scheduled and includes quick access to private data of Tx/Rx queue
52 * -1, if failed to allocate any resource.
59 for (i = 0; i < oct->num_oqs; i++) { in octep_alloc_ioq_vectors()
60 oct->ioq_vector[i] = vzalloc(sizeof(*oct->ioq_vector[i])); in octep_alloc_ioq_vectors()
61 if (!oct->ioq_vector[i]) in octep_alloc_ioq_vectors()
64 ioq_vector = oct->ioq_vector[i]; in octep_alloc_ioq_vectors()
65 ioq_vector->iq = oct->iq[i]; in octep_alloc_ioq_vectors()
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/linux/drivers/md/
H A Draid5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * RAID-4/5/6 management functions.
9 * Thanks to Penguin Computing for making the RAID-6 development possible
22 * conf->seq_write is the number of the last batch successfully written.
23 * conf->seq_flush is the number of the last batch that was closed to
26 * (in add_stripe_bio) we update the in-memory bitmap and record in sh->bm_seq
56 #include "md-bitmap.h"
57 #include "raid5-log.h"
74 static inline struct hlist_head *stripe_hash(struct r5conf *conf, sector_t sect) in stripe_hash() argument
76 int hash = (sect >> RAID5_STRIPE_SHIFT(conf)) & HASH_MASK; in stripe_hash()
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/linux/drivers/media/platform/ti/omap3isp/
H A Disphist.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Histogram module
28 * hist_reset_mem - clear Histogram memory before start stats engine.
32 struct isp_device *isp = hist->isp; in hist_reset_mem()
33 struct omap3isp_hist_config *conf = hist->priv; in hist_reset_mem() local
48 for (i = OMAP3ISP_HIST_MEM_SIZE / 4; i > 0; i--) { in hist_reset_mem()
56 hist->wait_acc_frames = conf->num_acc_frames; in hist_reset_mem()
60 * hist_setup_regs - Helper function to update Histogram registers.
64 struct isp_device *isp = hist->isp; in hist_setup_regs()
65 struct omap3isp_hist_config *conf = priv; in hist_setup_regs() local
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/linux/drivers/net/wireless/ti/wlcore/
H A Dacx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2009 Nokia Corporation
33 ret = -ENOMEM; in wl1271_acx_wake_up_conditions()
37 wake_up->role_id = wlvif->role_id; in wl1271_acx_wake_up_conditions()
38 wake_up->wake_up_event = wake_up_event; in wl1271_acx_wake_up_conditions()
39 wake_up->listen_interval = listen_interval; in wl1271_acx_wake_up_conditions()
62 ret = -ENOMEM; in wl1271_acx_sleep_auth()
66 auth->sleep_auth = sleep_auth; in wl1271_acx_sleep_auth()
75 wl->sleep_auth = sleep_auth; in wl1271_acx_sleep_auth()
91 return -EINVAL; in wl1271_acx_tx_power()
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/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
68 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
70 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
88 #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
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/linux/drivers/staging/vt6656/
H A Dmain_usb.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Purpose: driver entry for initial, open, close, tx and rx.
14 * vt6656_probe - module initial (insmod) driver entry
15 * vnt_free_tx_bufs - free tx buffer function
16 * vnt_init_registers- initial MAC & BBP & RF internal registers.
56 MODULE_PARM_DESC(tx_buffers, "Number of receive usb tx buffers");
80 /* Set number of TX buffers */ in vnt_set_options()
82 priv->num_tx_context = TX_DESC_DEF0; in vnt_set_options()
84 priv->num_tx_context = vnt_tx_buffers; in vnt_set_options()
88 priv->num_rcb = RX_DESC_DEF0; in vnt_set_options()
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