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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
[all …]
H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-sck-kv-g-revB.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
H A Dzynqmp-sck-kv-g-revA.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
8 * "A" – A01 board un-modified (NXP)
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/net/ti-dp83867.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 /dts-v1/;
23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
24 #address-cells = <1>;
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
[all …]
H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
[all …]
H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <dt-bindings/phy/phy.h>
[all …]
H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
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H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
42 phy-mode = "rgmii-id";
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/freebsd/sys/net80211/
H A Dieee80211_var.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
93 * says that VHT is supported - and then this macro can be
97 ((ic)->ic_flags_ext & IEEE80211_FEXT_VHT)
100 ((ic)->ic_flags_ext & IEEE80211_FEXT_SEQNO_OFFLOAD)
102 ((ic)->ic_flags_ext & IEEE80211_FEXT_FRAG_OFFLOAD)
106 * 1-1 to a physical device and one or more "Virtual AP's" (VAP)
116 * e.g. device-specific callbacks.
123 uint8_t ie_data[]; /* user-specified IE's */
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/freebsd/share/man/man4/
H A Dvte.435 .Bd -ragged -offset indent
42 .Xr loader.conf 5 :
43 .Bd -literal -offset indent
53 or half-duplex.
54 The controller supports interrupt moderation mechanism, a 64-bit multicast
55 hash filter, VLAN over-size frame and four station addresses.
64 .Bl -tag -width ".Cm 10baseT/UTP"
69 .Xr rc.conf 5 .
79 .Bl -tag -width ".Cm full-duplex"
80 .It Cm full-duplex
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H A Dgve.41 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
39 .Bd -ragged -offset indent
45 .Xr loader.conf 5 :
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
84 .Bl -diag
92 Global (across-queues) allocation failures:
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H A Daue.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
52 .Xr loader.conf 5 :
53 .Bd -literal -offset indent
63 will operate at 100Base-TX and full-duplex.
74 The Pegasus supports a 64-bit multicast hash table, single perfect
82 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
87 .Pa /etc/rc.conf
94 .Ar full-duplex
99 .Ar half-duplex
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H A Diavf.41 .\"-
2 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2013-2018, Intel Corporation
44 .Bd -ragged -offset indent
50 .Xr loader.conf 5 :
51 .Bd -literal -offset indent
62 .Bl -bullet -compact
64 Intel\(rg Ethernet Controller E810\-C
66 Intel\(rg Ethernet Controller E810\-XXV
68 Intel\(rg Ethernet Connection E822\-C
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H A Dxl.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
48 .Xr loader.conf 5 :
49 .Bd -literal -offset indent
57 and "tornado" bus-master Etherlink XL chips.
59 The Etherlink XL chips support built-in 10baseT, 10base2 and 10base5
63 NS 83840A 10/100 PHY for 10/100 Mbps support in full or half-duplex.
64 The 3c905B adapters have built-in autonegotiation logic mapped onto
67 adapters such as the 3c905-TX and 3c905B-TX are capable of 10 or
75 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
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H A Drl.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
48 .Xr loader.conf 5 :
49 .Bd -literal -offset indent
60 descriptor-based data transfer mechanism.
85 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
93 .Pa /etc/rc.conf
100 .Ar full-duplex
102 .Ar half-duplex
109 .Ar full-duplex
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986a-bananapi-bpi-r3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
18 model = "Bananapi BPI-R3";
19 chassis-type = "embedded";
20 compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
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/freebsd/crypto/openssl/crypto/rc4/asm/
H A Drc4-parisc.pl2 # Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved.
17 # RC4 for PA-RISC.
21 # Performance is 33% better than gcc 3.2 generated code on PA-7100LC.
23 # It's possible to unroll loop 8 times on PA-RISC 2.0, but improvement
26 # Special thanks to polarhome.com for providing HP-UX account.
60 if (open CONF,"<${dir}../../opensslconf.h") {
61 while(<CONF>) {
67 close CONF;
75 } else { # RC4_INT (~5% faster than RC4_CHAR on PA-7100LC)
88 @TX=("%r21","%r22");
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/freebsd/contrib/wpa/src/ap/
H A Dieee802_11_vht.c3 * Copyright (c) 2002-2009, Jouni Malinen <j@w1.fi>
27 struct hostapd_hw_modes *mode = hapd->iface->current_mode; in hostapd_eid_vht_capabilities()
30 if (!mode || is_6ghz_op_class(hapd->iconf->op_class)) in hostapd_eid_vht_capabilities()
33 if (mode->mode == HOSTAPD_MODE_IEEE80211G && hapd->conf->vendor_vht && in hostapd_eid_vht_capabilities()
34 mode->vht_capab == 0 && hapd->iface->hw_features) { in hostapd_eid_vht_capabilities()
37 for (i = 0; i < hapd->iface->num_hw_features; i++) { in hostapd_eid_vht_capabilities()
38 if (hapd->iface->hw_features[i].mode == in hostapd_eid_vht_capabilities()
40 mode = &hapd->iface->hw_features[i]; in hostapd_eid_vht_capabilities()
51 cap->vht_capabilities_info = host_to_le32( in hostapd_eid_vht_capabilities()
52 hapd->iface->conf->vht_capab); in hostapd_eid_vht_capabilities()
[all …]

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