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/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00config.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
24 struct rt2x00intf_conf conf; in rt2x00lib_config_intf() local
27 conf.type = type; in rt2x00lib_config_intf()
31 conf.sync = TSF_SYNC_ADHOC; in rt2x00lib_config_intf()
35 conf.sync = TSF_SYNC_AP_NONE; in rt2x00lib_config_intf()
38 conf.sync = TSF_SYNC_INFRA; in rt2x00lib_config_intf()
41 conf.sync = TSF_SYNC_NONE; in rt2x00lib_config_intf()
51 memset(conf.mac, 0, sizeof(conf.mac)); in rt2x00lib_config_intf()
53 memcpy(conf.mac, mac, ETH_ALEN); in rt2x00lib_config_intf()
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
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H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
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H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
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/linux/drivers/isdn/mISDN/
H A Ddsp_cmx.c20 * There are 3 different solutions: -1 = software, 0 = hardware-crossconnect
21 * 1-n = hardware-conference. The n will give the conference number.
39 * - Crossconnecting or even conference, if more than two members are together.
40 * - Force mixing of transmit data with other crossconnect/conference members.
41 * - Echo generation to benchmark the delay of audio processing.
42 * - Use hardware to minimize cpu load, disable FIFO load and minimize delay.
43 * - Dejittering and clock generation.
48 * RX-Buffer
51 * ----------------+-------------+-------------------
53 * The rx-buffer is a ring buffer used to store the received data for each
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/linux/drivers/net/wireless/ti/wlcore/
H A Dacx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2009 Nokia Corporation
33 ret = -ENOMEM; in wl1271_acx_wake_up_conditions()
37 wake_up->role_id = wlvif->role_id; in wl1271_acx_wake_up_conditions()
38 wake_up->wake_up_event = wake_up_event; in wl1271_acx_wake_up_conditions()
39 wake_up->listen_interval = listen_interval; in wl1271_acx_wake_up_conditions()
62 ret = -ENOMEM; in wl1271_acx_sleep_auth()
66 auth->sleep_auth = sleep_auth; in wl1271_acx_sleep_auth()
75 wl->sleep_auth = sleep_auth; in wl1271_acx_sleep_auth()
91 return -EINVAL; in wl1271_acx_tx_power()
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cn9k.c1 // SPDX-License-Identifier: GPL-2.0
19 struct device *dev = &oct->pdev->dev; in cn93_vf_dump_q_regs()
21 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
50 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
85 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cn93_vf_reset_iq()
105 /* Reset Hardware Rx queue */
110 /* Disable Output (Rx) Ring */ in cn93_vf_reset_oq()
121 /* Reset all hardware Tx/Rx queues */
124 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cn93()
127 dev_dbg(&pdev->dev, "Reset OCTEP_CN93 VF IO Queues\n"); in octep_vf_reset_io_queues_cn93()
[all …]
H A Doctep_vf_cnxk.c1 // SPDX-License-Identifier: GPL-2.0
19 struct device *dev = &oct->pdev->dev; in cnxk_vf_dump_q_regs()
21 dev_info(dev, "IQ-%d register dump\n", qno); in cnxk_vf_dump_q_regs()
50 dev_info(dev, "OQ-%d register dump\n", qno); in cnxk_vf_dump_q_regs()
88 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cnxk_vf_reset_iq()
107 /* Reset Hardware Rx queue */
112 /* Disable Output (Rx) Ring */ in cnxk_vf_reset_oq()
123 /* Reset all hardware Tx/Rx queues */
126 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cnxk()
129 dev_dbg(&pdev->dev, "Reset OCTEP_CNXK VF IO Queues\n"); in octep_vf_reset_io_queues_cnxk()
[all …]
/linux/net/mac80211/
H A Dwep.c1 // SPDX-License-Identifier: GPL-2.0-only
29 get_random_bytes(&local->wep_iv, IEEE80211_WEP_IV_LEN); in ieee80211_wep_init()
51 local->wep_iv++; in ieee80211_wep_get_iv()
52 if (ieee80211_wep_weak_iv(local->wep_iv, keylen)) in ieee80211_wep_get_iv()
53 local->wep_iv += 0x0100; in ieee80211_wep_get_iv()
58 *iv++ = (local->wep_iv >> 16) & 0xff; in ieee80211_wep_get_iv()
59 *iv++ = (local->wep_iv >> 8) & 0xff; in ieee80211_wep_get_iv()
60 *iv++ = local->wep_iv & 0xff; in ieee80211_wep_get_iv()
69 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; in ieee80211_wep_add_iv()
74 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PROTECTED); in ieee80211_wep_add_iv()
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/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_cn9k_pf.c1 // SPDX-License-Identifier: GPL-2.0
19 /* Names of Hardware non-queue generic interrupts */
42 struct device *dev = &oct->pdev->dev; in cn93_dump_regs()
44 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_dump_regs()
73 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_dump_regs()
109 struct octep_config *conf = oct->conf; in cn93_reset_iq() local
112 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); in cn93_reset_iq()
115 q_no += conf->pf_ring_cfg.srn; in cn93_reset_iq()
134 /* Reset Hardware Rx queue */
139 q_no += CFG_GET_PORTS_PF_SRN(oct->conf); in cn93_reset_oq()
[all …]
H A Doctep_cnxk_pf.c1 // SPDX-License-Identifier: GPL-2.0
20 /* Names of Hardware non-queue generic interrupts */
62 struct device *dev = &oct->pdev->dev; in cnxk_dump_regs()
64 dev_info(dev, "IQ-%d register dump\n", qno); in cnxk_dump_regs()
93 dev_info(dev, "OQ-%d register dump\n", qno); in cnxk_dump_regs()
129 struct octep_config *conf = oct->conf; in cnxk_reset_iq() local
132 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); in cnxk_reset_iq()
135 q_no += conf->pf_ring_cfg.srn; in cnxk_reset_iq()
154 /* Reset Hardware Rx queue */
159 q_no += CFG_GET_PORTS_PF_SRN(oct->conf); in cnxk_reset_oq()
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/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
71 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
73 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
74 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
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H A Dspi-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Mika Westerberg
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
65 /* maximum depth of RX/TX FIFO */
69 * struct ep93xx_spi - EP93xx SPI controller structure
74 * @rx: current byte in transfer to receive
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
[all …]
H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
42 phy-mode = "rgmii-id";
[all …]
/linux/drivers/tty/serial/
H A Dmax3100.c1 // SPDX-License-Identifier: GPL-2.0+
7 * writing conf clears FIFO buffer and we cannot have this interrupt
10 * The initial minor number is 209 in the low-density serial port:
87 int conf; /* configuration for the MAX31000 member
88 * (bits 0-7, bits 8-11 are irqs) */
97 int rx_enabled; /* if we should rx chars */
126 if (s->parity & MAX3100_PARITY_ODD) in max3100_do_parity()
131 if (s->parity & MAX3100_7BIT) in max3100_do_parity()
147 if (s->parity & MAX3100_7BIT) in max3100_calc_parity()
152 if (s->parity & MAX3100_PARITY_ON) in max3100_calc_parity()
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H A Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
169 } rx; member
198 writel_relaxed(val, port->membase + off); in msm_write()
204 return readl_relaxed(port->membase + off); in msm_read()
216 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
228 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
239 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
242 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
244 else if (port->uartclk == 4800000) in msm_serial_set_mnd_regs()
[all …]
/linux/drivers/net/wireless/ti/wl18xx/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2011-2012 Texas Instruments
83 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_beacon_early_term, "%u");
84 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_out_of_mpdu_nodes, "%u");
85 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_hdr_overflow, "%u");
86 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_dropped_frame, "%u");
87 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_done, "%u");
88 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_defrag, "%u");
89 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_defrag_end, "%u");
90 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_cmplt, "%u");
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-bananapi-bpi-r3-mini.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Authors: Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
19 model = "Bananapi BPI-R3 Mini";
20 chassis-type = "embedded";
21 compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a";
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/linux/tools/testing/selftests/drivers/net/microchip/
H A Dksz9477_qos.sh2 # SPDX-License-Identifier: GPL-2.0
36 sysctl_set net.ipv6.conf.${h1}.disable_ipv6 1
38 h1_mac=$(ip -j link show dev ${h1} | jq -e '.[].address')
43 sysctl_restore net.ipv6.conf.${h1}.disable_ipv6
50 sysctl_set net.ipv6.conf.${h2}.disable_ipv6 1
51 h2_mac=$(ip -j link show dev ${h2} | jq -e '.[].address')
56 sysctl_restore net.ipv6.conf.${h2}.disable_ipv6
64 sysctl_set net.ipv6.conf.${swp1}.disable_ipv6 1
65 sysctl_set net.ipv6.conf.${swp2}.disable_ipv6 1
72 sysctl_set net.ipv6.conf.br0.disable_ipv6 1
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