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/freebsd/contrib/wpa/src/ap/
H A Dacs.c2 * ACS - Automatic Channel Selection module
31 * ------------
35 * ----------
36 * - make sure you have CONFIG_ACS=y in hostapd's .config
37 * - use channel=0 or channel=acs to enable ACS
40 * ----------------
48 * -----------------
49 * - Current implementation depends heavily on the amount of time willing to
52 * - Ideal channel may end up overlapping a channel with 40 MHz intolerant BSS
55 * ------------
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H A Dwpa_auth_ft.c2 * hostapd - IEEE 802.11r - Fast BSS Transition
3 * Copyright (c) 2004-2018, Jouni Malinen <j@w1.fi>
58 * wpa_ft_rrb_decrypt - Decrypt FT RRB message
59 * @key: AES-SIV key for AEAD
66 * @type: Vendor-specific subtype of the RRB frame (FT_PACKET_*)
72 * Returns: 0 on success, -1 on error
105 *plain = os_zalloc(enc_len - AES_BLOCK_SIZE); in wpa_ft_rrb_decrypt()
117 enc_len -= 2; in wpa_ft_rrb_decrypt()
123 *plain_size = enc_len - AES_BLOCK_SIZE; in wpa_ft_rrb_decrypt()
134 return -1; in wpa_ft_rrb_decrypt()
[all …]
H A Dieee802_11_vht.c3 * Copyright (c) 2002-2009, Jouni Malinen <j@w1.fi>
27 struct hostapd_hw_modes *mode = hapd->iface->current_mode; in hostapd_eid_vht_capabilities()
30 if (!mode || is_6ghz_op_class(hapd->iconf->op_class)) in hostapd_eid_vht_capabilities()
33 if (mode->mode == HOSTAPD_MODE_IEEE80211G && hapd->conf->vendor_vht && in hostapd_eid_vht_capabilities()
34 mode->vht_capab == 0 && hapd->iface->hw_features) { in hostapd_eid_vht_capabilities()
37 for (i = 0; i < hapd->iface->num_hw_features; i++) { in hostapd_eid_vht_capabilities()
38 if (hapd->iface->hw_features[i].mode == in hostapd_eid_vht_capabilities()
40 mode = &hapd->iface->hw_features[i]; in hostapd_eid_vht_capabilities()
51 cap->vht_capabilities_info = host_to_le32( in hostapd_eid_vht_capabilities()
52 hapd->iface->conf->vht_capab); in hostapd_eid_vht_capabilities()
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-sck-kv-g-revB.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dzynqmp-sck-kv-g-revA.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
8 * "A" – A01 board un-modified (NXP)
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/net/ti-dp83867.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 /dts-v1/;
23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
24 #address-cells = <1>;
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <dt-bindings/phy/phy.h>
[all …]
H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
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H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
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H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
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/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
31 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
37 switch-14 {
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
40 ps-clk-frequency = <33333333>;
45 phy-mode = "rgmii-id";
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/freebsd/share/man/man4/
H A Dgve.41 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
39 .Bd -ragged -offset indent
45 .Xr loader.conf 5 :
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
87 Change the RX queue count to 4 for the gve0 interface:
93 Change the RX ring size to 512 for the gve0 interface:
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H A Diavf.41 .\"-
2 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2013-2018, Intel Corporation
44 .Bd -ragged -offset indent
50 .Xr loader.conf 5 :
51 .Bd -literal -offset indent
62 .Bl -bullet -compact
64 Intel\(rg Ethernet Controller E810\-C
66 Intel\(rg Ethernet Controller E810\-XXV
68 Intel\(rg Ethernet Connection E822\-C
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H A Duftdi.42 .\" SPDX-License-Identifier: BSD-2-Clause
45 .Xr rc.conf 5 :
49 .Xr sysctl.conf 5 :
62 .Xr rc.conf 5 ,
80 .Bl -bullet -compact
104 .Xr loader.conf 5 ,
105 .Xr sysctl.conf 5 ,
108 .Bl -tag -width "hw.usb.uftdi.skip_jtag_interfaces"
125 .Bl -tag -width indent
127 Reset the channel to its default configuration, flush RX and TX FIFOs.
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/freebsd/sys/net80211/
H A Dieee80211_var.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
93 * says that VHT is supported - and then this macro can be
97 ((ic)->ic_flags_ext & IEEE80211_FEXT_VHT)
100 ((ic)->ic_flags_ext & IEEE80211_FEXT_SEQNO_OFFLOAD)
102 ((ic)->ic_flags_ext & IEEE80211_FEXT_FRAG_OFFLOAD)
104 ((ic)->ic_flags_ext & IEEE80211_FEXT_AMPDU_OFFLOAD)
108 * 1-1 to a physical device and one or more "Virtual AP's" (VAP)
118 * e.g. device-specific callbacks.
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986a-bananapi-bpi-r3-mini.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Authors: Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
19 model = "Bananapi BPI-R3 Mini";
20 chassis-type = "embedded";
21 compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a";
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_config.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
284 * (in AXI beats-128b) (5b)
315 /** UDMA per queue Target-ID control configuration */
317 /* Enable usage of the Target-ID per queue according to 'tgtid' */
320 /* Enable usage of the Target-ID from the descriptor buffer address 63:48 */
323 /* Target-ID to be applied when 'queue_en' is asserted */
331 /** UDMA Target-ID control configuration */
336 /* RX queue configuration */
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/freebsd/sys/contrib/dev/iwlwifi/mld/
H A Dmld.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2024-2025 Intel Corporation
8 #include "fw/api/rx.h"
29 #include "iwl-nvm-parse.h"
57 struct wiphy *wiphy = mld->wiphy; in iwl_mld_hw_set_regulatory()
59 wiphy->regulatory_flags |= REGULATORY_WIPHY_SELF_MANAGED; in iwl_mld_hw_set_regulatory()
60 wiphy->regulatory_flags |= REGULATORY_ENABLE_RELAX_NO_IR; in iwl_mld_hw_set_regulatory()
68 mld->dev = trans->dev; in iwl_construct_mld()
69 mld->trans = trans; in iwl_construct_mld()
70 mld->cfg = cfg; in iwl_construct_mld()
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