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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad4695.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/linux/net/ncsi/
H A Dncsi-rsp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "ncsi-pkt.h"
20 #include "ncsi-netlink.h"
46 h = (struct ncsi_rsp_pkt_hdr *)skb_network_header(nr->rsp); in ncsi_validate_rsp_pkt()
48 if (h->common.revision != NCSI_PKT_REVISION) { in ncsi_validate_rsp_pkt()
49 netdev_dbg(nr->ndp->ndev.dev, in ncsi_validate_rsp_pkt()
51 return -EINVAL; in ncsi_validate_rsp_pkt()
53 if (ntohs(h->common.length) != payload) { in ncsi_validate_rsp_pkt()
54 netdev_dbg(nr->ndp->ndev.dev, in ncsi_validate_rsp_pkt()
56 return -EINVAL; in ncsi_validate_rsp_pkt()
[all …]
H A Dncsi-pkt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 unsigned char revision; /* NCSI version - 0x01 */
15 unsigned char channel; /* Network controller ID */ member
21 struct ncsi_pkt_hdr common; /* Common NCSI packet header */ member
25 struct ncsi_pkt_hdr common; /* Common NCSI packet header */ member
31 struct ncsi_pkt_hdr common; /* Common NCSI packet header */ member
36 /* NCSI common command packet */
58 /* Disable Channel */
67 /* Reset Channel */
80 __be32 mode; /* AEN working mode */ member
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/linux/arch/arm/mach-omap2/
H A Dvc.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "prm-regbits-34xx.h"
20 #include "prm-regbits-44xx.h"
52 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
59 * Channel configuration bits, common for OMAP3+
82 * configuration, except the OMAP4 MPU channel. This appears
83 * to be a freak accident as every other VC channel has the
84 * default configuration, thus creating a mutant channel config.
101 * omap_vc_config_channel - configure VC channel to PMIC mappings
102 * @voltdm: pointer to voltagdomain defining the desired VC channel
[all …]
H A Dvc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
35 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
63 * struct omap_vc_channel - VC per-instance data
64 * @i2c_slave_addr: I2C slave address of PMIC for this VC channel
67 * @setup_time: setup time (in sys_clk cycles) of regulator for this channel
68 * @cfg_channel: current value of VC channel configuration register
69 * @i2c_high_speed: whether or not to use I2C high-speed mode
71 * @common: pointer to VC common data for this platform
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/linux/Documentation/devicetree/bindings/display/
H A Ddsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for DSI Display Panels
10 - Linus Walleij <linus.walleij@linaro.org>
13 This document defines device tree properties common to DSI, Display
25 channel should have a node "panel" for their virtual channel with their
26 reg-property set to the virtual channel number, usually there is just
27 one virtual channel, number 0.
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/linux/Documentation/devicetree/bindings/leds/
H A Dleds-lp55xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp55xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
14 Bindings for the TI/National Semiconductor LP55xx and LP8501 multi channel
27 - national,lp5521
28 - national,lp5523
29 - ti,lp55231
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H A Drichtek,rt8515.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Richtek RT8515 1.5A dual channel LED driver
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Richtek RT8515 is a dual channel (two mode) LED driver that
14 supports driving a white LED in flash or torch mode. The maximum
15 current for each mode is defined in hardware using two resistors
22 enf-gpios:
26 ent-gpios:
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/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_phy.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
125 * ar9003_hw_set_channel - set channel on single-chip device
129 * This is the function to change channel on single-chip devices, that is
132 * This function takes the channel value in MHz and sets
133 * hardware channel value. Assumes writes have been enabled to analog bus.
137 * For 2GHz channel,
138 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
141 * For 5GHz channel,
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/linux/drivers/net/can/rcar/
H A Drcar_canfd.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8 * - CAN FD only mode
9 * - Classical CAN (CAN 2.0) only mode
11 * This driver puts the controller in CAN FD only mode by default. In this
12 * mode, the controller acts as a CAN FD node that can also interoperate with
15 * To switch the controller to Classical CAN (CAN 2.0) only mode, add
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
73 /* Non-operational status */
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/linux/Documentation/iio/
H A Dad4695.rst1 .. SPDX-License-Identifier: GPL-2.0-only
26 ------
[all...]
/linux/drivers/net/wireless/ath/ath5k/
H A Dreset.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
30 #include <linux/pci.h> /* To determine if a card is pci-e */
52 * ath5k_hw_register_timeout() - Poll a register for a flag/field change
64 * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
73 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { in ath5k_hw_register_timeout()
82 return (i <= 0) ? -EAGAIN : 0; in ath5k_hw_register_timeout()
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H A Dath5k.h2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
21 /* TODO: Clean up channel debugging (doesn't work anyway) and start
40 * and clean up common bits, then introduce set/get functions in eeprom.c */
62 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
63 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
70 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
72 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
189 #define AR5K_TUNE_NOISE_FLOOR -72
190 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
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/linux/drivers/net/wireless/rsi/
H A Drsi_91x_mgmt.c268 * rsi_set_default_parameters() - This function sets default parameters.
269 * @common: Pointer to the driver private structure.
273 static void rsi_set_default_parameters(struct rsi_common *common) in rsi_set_default_parameters() argument
275 common->band = NL80211_BAND_2GHZ; in rsi_set_default_parameters()
276 common->channel_width = BW_20MHZ; in rsi_set_default_parameters()
277 common->rts_threshold = IEEE80211_MAX_RTS_THRESHOLD; in rsi_set_default_parameters()
278 common->channel = 1; in rsi_set_default_parameters()
279 memset(&common->rate_config, 0, sizeof(common->rate_config)); in rsi_set_default_parameters()
280 common->fsm_state = FSM_CARD_NOT_READY; in rsi_set_default_parameters()
281 common->iface_down = true; in rsi_set_default_parameters()
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/linux/drivers/media/platform/ti/davinci/
H A Dvpif_capture.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-ioctl.h>
19 #include <media/v4l2-mediabus.h>
38 MODULE_PARM_DESC(debug, "Debug level 0-1");
71 struct vb2_queue *q = vb->vb2_queue; in vpif_buffer_prepare()
73 struct common_obj *common; in vpif_buffer_prepare() local
78 common = &ch->common[VPIF_VIDEO_INDEX]; in vpif_buffer_prepare()
80 vb2_set_plane_payload(vb, 0, common->fmt.fmt.pix.sizeimage); in vpif_buffer_prepare()
82 return -EINVAL; in vpif_buffer_prepare()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dmicrochip,sama7g5-i2smcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip I2S Multi-Channel Controller
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
13 The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and
15 multi-channel audio codecs. It consists of a receiver, a transmitter and a
16 common clock generator that can be enabled separately to provide Adapter,
19 multi-channel is supported by using multiple data pins, output and
[all …]
H A Ddavinci-mcasp-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,dm646x-mcasp-audio
16 - ti,da830-mcasp-audio
17 - ti,am33xx-mcasp-audio
18 - ti,dra7-mcasp-audio
19 - ti,omap4-mcasp-audio
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H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
15 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
16 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
17 playback and DMA channel 3 for capture. The developer can choose which
18 DMA controller to use, but the channels themselves are hard-wired. The
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-adc-hi84357 Could be either "GND-Open" or "Supply-Open" mode. Y is a
8 threshold detector input channel. Channels 0..7, 8..15, 16..23
9 and 24..31 has common sensor types.
16 Channel Y low voltage threshold. If sensor input voltage goes lower then
19 is separately set for "GND-Open" and "Supply-Open" modes.
20 Channels 0..31 have common low threshold values, but could have different
35 Channel Y high voltage threshold. If sensor input voltage goes higher then
38 is separately set for "GND-Open" and "Supply-Open" modes.
40 Channels 0..31 have common high threshold values, but could have different
/linux/drivers/media/i2c/
H A Dov772x.c1 // SPDX-License-Identifier: GPL-2.0
12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
26 #include <linux/v4l2-mediabus.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-subdev.h>
41 #define GAIN 0x00 /* AGC - Gain control gain setting */
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-props.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common properties for LPDDR types
11 range of legal values for each. This file defines the common parts that can be
13 an LPDDR channel node.
16 - Krzysztof Kozlowski <krzk@kernel.org>
23 lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
32 channel.
[all …]
/linux/Documentation/hwmon/
H A Dpcf8591.rst17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
35 - mode 1 : three differential inputs
36 Pins AIN3 is the common negative differential input
39 - mode 2 : single ended and differential mixed
[all …]
/linux/drivers/iio/adc/
H A Dad4695.c1 // SPDX-License-Identifier: GPL-2.0-only
33 #include <dt-bindings/iio/adc/adi,ad4695.h>
83 /* Conversion mode commands */
116 unsigned int channel; member
134 /* Common mode input pin voltage. */
189 .name = "ad4695-8",
219 .name = "ad4695-16",
296 * ad4695_set_single_cycle_mode - Set the device in single cycle mode
298 * @channel: The first channel to read
300 * As per the datasheet, to enable single cycle mode, we need to set
[all …]
/linux/Documentation/driver-api/
H A Dedac.rst5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
13 creating a common ground for discussion, terms and their definitions
35 * Channel
37 A memory controller channel, responsible to communicate with a group of
38 DIMMs. Each channel has its own independent control (command) and data
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
26 if (axi->axi_lpi_en) in dwmac4_dma_axi()
28 if (axi->axi_xit_frm) in dwmac4_dma_axi()
32 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
36 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
44 switch (axi->axi_blen[i]) { in dwmac4_dma_axi()
77 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; in dwmac4_dma_init_rx_chan()
79 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; in dwmac4_dma_init_rx_chan()
85 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) in dwmac4_dma_init_rx_chan()
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