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/linux/drivers/dma/
H A Dfsldma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
18 * command. Please be aware that this setting may result in read pre-fetching
29 #include <linux/dma-mapping.h>
40 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
42 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
52 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32); in set_sr()
57 return FSL_DMA_IN(chan, &chan->regs->sr, 32); in get_sr()
62 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32); in set_mr()
67 return FSL_DMA_IN(chan, &chan->regs->mr, 32); in get_mr()
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/linux/net/ncsi/
H A Dncsi-rsp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "ncsi-pkt.h"
20 #include "ncsi-netlink.h"
46 h = (struct ncsi_rsp_pkt_hdr *)skb_network_header(nr->rsp); in ncsi_validate_rsp_pkt()
48 if (h->common in ncsi_validate_rsp_pkt()
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H A Dncsi-pkt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 unsigned char revision; /* NCSI version - 0x01 */
15 unsigned char channel; /* Network controller ID */ member
21 struct ncsi_pkt_hdr common; /* Common NCSI packet header */ member
25 struct ncsi_pkt_hdr common; /* Commo member
31 struct ncsi_pkt_hdr common; /* Common NCSI packet header */ global() member
80 __be32 mode; /* AEN working mode */ global() member
88 __be32 mode; /* Link working mode */ global() member
110 unsigned char mode; /* VLAN filter mode */ global() member
128 __be32 mode; /* Filter mode */ global() member
136 __be32 mode; /* Global MC mode */ global() member
145 unsigned char mode; /* Flow control mode */ global() member
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/linux/arch/arm/mach-omap2/
H A Dvc.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "prm-regbits-34xx.h"
20 #include "prm-regbits-44xx.h"
52 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
59 * Channel configuration bits, common for OMAP3+
82 * configuration, except the OMAP4 MPU channel. This appears
83 * to be a freak accident as every other VC channel has the
84 * default configuration, thus creating a mutant channel config.
101 * omap_vc_config_channel - configure VC channel to PMIC mappings
102 * @voltdm: pointer to voltagdomain defining the desired VC channel
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H A Dvc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
35 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
63 * struct omap_vc_channel - VC per-instance data
64 * @i2c_slave_addr: I2C slave address of PMIC for this VC channel
67 * @setup_time: setup time (in sys_clk cycles) of regulator for this channel
68 * @cfg_channel: current value of VC channel configuration register
69 * @i2c_high_speed: whether or not to use I2C high-speed mode
71 * @common: pointer to VC common data for this platform
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/linux/drivers/iio/adc/
H A Dad4030.c1 // SPDX-License-Identifier: GPL-2.0-only
93 * This accounts for 1 sample per channel plus one s64 for the timestamp,
109 #define AD4030_TCYC_ADJUSTED_NS (AD4030_TCYC_NS - AD4030_TCNVL_NS)
112 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS)
155 enum ad4030_out_mode mode; member
166 u8 common; member
170 u8 common[2]; member
176 * For a chip with 2 hardware channel this will be used to create 2 common-mode
178 * - voltage4
179 * - voltage5
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/linux/Documentation/devicetree/bindings/display/
H A Ddsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for DSI Display Panels
10 - Linus Walleij <linus.walleij@linaro.org>
13 This document defines device tree properties common to DSI, Display
25 channel should have a node "panel" for their virtual channel with their
26 reg-property set to the virtual channel number, usually there is just
27 one virtual channel, number 0.
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad7380.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
21 * https://www.analog.com/en/products/ad7380-4.html
22 * https://www.analog.com/en/products/ad7381-4.html
23 * https://www.analog.com/en/products/ad7383-4.html
24 * https://www.analog.com/en/products/ad7384-4.html
25 * https://www.analog.com/en/products/ad7386-4.html
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/linux/Documentation/devicetree/bindings/leds/
H A Dleds-lp55xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp55xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
14 Bindings for the TI/National Semiconductor LP55xx and LP8501 multi channel
27 - national,lp5521
28 - national,lp5523
29 - ti,lp55231
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H A Drichtek,rt8515.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Richtek RT8515 1.5A dual channel LED driver
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Richtek RT8515 is a dual channel (two mode) LED driver that
14 supports driving a white LED in flash or torch mode. The maximum
15 current for each mode is defined in hardware using two resistors
22 enf-gpios:
26 ent-gpios:
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/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_phy.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
125 * ar9003_hw_set_channel - set channel on single-chip device
129 * This is the function to change channel on single-chip devices, that is
132 * This function takes the channel value in MHz and sets
133 * hardware channel value. Assumes writes have been enabled to analog bus.
137 * For 2GHz channel,
138 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
141 * For 5GHz channel,
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H A Dhtc_drv_main.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
34 enum ath9k_power_mode mode) in ath9k_htc_setpower() argument
38 mutex_lock(&priv->htc_pm_lock); in ath9k_htc_setpower()
39 ret = ath9k_hw_setpower(priv->ah, mode); in ath9k_htc_setpower()
40 mutex_unlock(&priv->htc_pm_lock); in ath9k_htc_setpower()
47 mutex_lock(&priv->htc_pm_lock); in ath9k_htc_ps_wakeup()
48 if (++priv->ps_usecount != 1) in ath9k_htc_ps_wakeup()
50 ath9k_hw_setpower(priv->ah, ATH9K_PM_AWAKE); in ath9k_htc_ps_wakeup()
53 mutex_unlock(&priv->htc_pm_lock); in ath9k_htc_ps_wakeup()
60 mutex_lock(&priv->htc_pm_lock); in ath9k_htc_ps_restore()
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/linux/drivers/net/wireless/ath/ath5k/
H A Dreset.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
30 #include <linux/pci.h> /* To determine if a card is pci-e */
52 * ath5k_hw_register_timeout() - Poll a register for a flag/field change
64 * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
73 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { in ath5k_hw_register_timeout()
82 return (i <= 0) ? -EAGAIN : 0; in ath5k_hw_register_timeout()
[all …]
H A Dath5k.h2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
21 /* TODO: Clean up channel debugging (doesn't work anyway) and start
40 * and clean up common bits, then introduce set/get functions in eeprom.c */
62 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
63 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
70 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
72 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
189 #define AR5K_TUNE_NOISE_FLOOR -72
190 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
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/linux/drivers/net/wireless/rsi/
H A Drsi_91x_mgmt.c268 * rsi_set_default_parameters() - This function sets default parameters.
269 * @common: Pointer to the driver private structure.
273 static void rsi_set_default_parameters(struct rsi_common *common) in rsi_set_default_parameters() argument
275 common->band = NL80211_BAND_2GHZ; in rsi_set_default_parameters()
276 common->channel_width = BW_20MHZ; in rsi_set_default_parameters()
277 common->rts_threshold = IEEE80211_MAX_RTS_THRESHOLD; in rsi_set_default_parameters()
278 common->channel = 1; in rsi_set_default_parameters()
279 memset(&common->rate_config, 0, sizeof(common->rate_config)); in rsi_set_default_parameters()
280 common->fsm_state = FSM_CARD_NOT_READY; in rsi_set_default_parameters()
281 common->iface_down = true; in rsi_set_default_parameters()
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/linux/Documentation/devicetree/bindings/sound/
H A Dmicrochip,sama7g5-i2smcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip I2S Multi-Channel Controller
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
13 The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and
15 multi-channel audio codecs. It consists of a receiver, a transmitter and a
16 common clock generator that can be enabled separately to provide Adapter,
19 multi-channel is supported by using multiple data pins, output and
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H A Ddavinci-mcasp-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,dm646x-mcasp-audio
16 - ti,da830-mcasp-audio
17 - ti,am33xx-mcasp-audio
18 - ti,dra7-mcasp-audio
19 - ti,omap4-mcasp-audio
[all …]
/linux/drivers/media/platform/ti/davinci/
H A Dvpif_capture.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-ioctl.h>
19 #include <media/v4l2-mediabus.h>
38 MODULE_PARM_DESC(debug, "Debug level 0-1");
71 struct vb2_queue *q = vb->vb2_queue; in vpif_buffer_prepare()
73 struct common_obj *common; in vpif_buffer_prepare() local
78 common = &ch->common[VPIF_VIDEO_INDEX]; in vpif_buffer_prepare()
80 vb2_set_plane_payload(vb, 0, common->fmt.fmt.pix.sizeimage); in vpif_buffer_prepare()
82 return -EINVAL; in vpif_buffer_prepare()
[all …]
/linux/drivers/dma/xilinx/
H A Dxilinx_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
14 * and write (MM2S) channel operation. It can be configured to have either
15 * one channel or two channels. If configured as two channels, one is to
18 * registers are accessed through an AXI4-Lite slave interface.
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
23 * transmit channel, both of them optional at synthesis time.
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-adc-hi84357 Could be either "GND-Open" or "Supply-Open" mode. Y is a
8 threshold detector input channel. Channels 0..7, 8..15, 16..23
9 and 24..31 has common sensor types.
16 Channel Y low voltage threshold. If sensor input voltage goes lower then
19 is separately set for "GND-Open" and "Supply-Open" modes.
20 Channels 0..31 have common low threshold values, but could have different
35 Channel Y high voltage threshold. If sensor input voltage goes higher then
38 is separately set for "GND-Open" and "Supply-Open" modes.
40 Channels 0..31 have common high threshold values, but could have different
/linux/drivers/media/i2c/
H A Dov772x.c1 // SPDX-License-Identifier: GPL-2.0
12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
26 #include <linux/v4l2-mediabus.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-subdev.h>
41 #define GAIN 0x00 /* AGC - Gain control gain setting */
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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-props.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common properties for LPDDR types
11 range of legal values for each. This file defines the common parts that can be
13 an LPDDR channel node.
16 - Krzysztof Kozlowski <krzk@kernel.org>
23 lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
32 channel.
[all …]
/linux/Documentation/hwmon/
H A Dpcf8591.rst17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
35 - mode 1 : three differential inputs
36 Pins AIN3 is the common negative differential input
39 - mode 2 : single ended and differential mixed
[all …]
/linux/include/linux/
H A Dieee80211.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
7 * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
10 * Copyright (c) 2013 - 2014 Intel Mobile Communications GmbH
11 * Copyright (c) 2016 - 2017 Intel Deutschland GmbH
12 * Copyright (c) 2018 - 2024 Intel Corporation
34 * -----------------------------------------------------------------
35 * 0 0 DA SA BSSID - IBSS/DLS
36 * 0 1 DA BSSID SA - AP -> STA
37 * 1 0 BSSID SA DA - AP <- STA
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
26 if (axi->axi_lpi_en) in dwmac4_dma_axi()
28 if (axi->axi_xit_frm) in dwmac4_dma_axi()
32 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
36 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
44 switch (axi->axi_blen[i]) { in dwmac4_dma_axi()
77 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; in dwmac4_dma_init_rx_chan()
79 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; in dwmac4_dma_init_rx_chan()
85 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) in dwmac4_dma_init_rx_chan()
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