Lines Matching +full:common +full:- +full:mode +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-only
93 * This accounts for 1 sample per channel plus one s64 for the timestamp,
109 #define AD4030_TCYC_ADJUSTED_NS (AD4030_TCYC_NS - AD4030_TCNVL_NS)
112 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS)
155 enum ad4030_out_mode mode; member
166 u8 common; member
170 u8 common[2]; member
176 * For a chip with 2 hardware channel this will be used to create 2 common-mode
178 * - voltage4
179 * - voltage5
180 * As the common-mode channels are after the differential ones, we compute the
181 * channel number like this:
182 * - _idx is the scan_index (the order in the output buffer)
183 * - _ch is the hardware channel number this common-mode channel is related
184 * - _idx - _ch gives us the number of channel in the chip
185 * - _idx - _ch * 2 is the starting number of the common-mode channels, since
186 * for each differential channel there is a common-mode channel
187 * - _idx - _ch * 2 + _ch gives the channel number for this specific common-mode
188 * channel
196 .channel = ((_idx) - (_ch)) * 2 + (_ch), \
207 * For a chip with 2 hardware channel this will be used to create 2 differential
209 * - voltage0-voltage1
210 * - voltage2-voltage3
226 .channel = (_idx) * 2, \
243 st->tx_data[0] = AD4030_REG_ACCESS; in ad4030_enter_config_mode()
246 .tx_buf = st->tx_data, in ad4030_enter_config_mode()
251 return spi_sync_transfer(st->spi, &xfer, 1); in ad4030_enter_config_mode()
256 st->tx_data[0] = 0; in ad4030_exit_config_mode()
257 st->tx_data[1] = AD4030_REG_EXIT_CFG_MODE; in ad4030_exit_config_mode()
258 st->tx_data[2] = AD4030_REG_EXIT_CFG_MODE_EXIT_MSK; in ad4030_exit_config_mode()
261 .tx_buf = st->tx_data, in ad4030_exit_config_mode()
266 return spi_sync_transfer(st->spi, &xfer, 1); in ad4030_exit_config_mode()
275 .tx_buf = st->tx_data, in ad4030_spi_read()
276 .rx_buf = st->rx_data.raw, in ad4030_spi_read()
281 if (xfer.len > sizeof(st->tx_data) || in ad4030_spi_read()
282 xfer.len > sizeof(st->rx_data.raw)) in ad4030_spi_read()
283 return -EINVAL; in ad4030_spi_read()
289 memset(st->tx_data, 0, sizeof(st->tx_data)); in ad4030_spi_read()
290 memcpy(st->tx_data, reg, reg_size); in ad4030_spi_read()
292 ret = spi_sync_transfer(st->spi, &xfer, 1); in ad4030_spi_read()
296 memcpy(val, &st->rx_data.raw[reg_size], val_size); in ad4030_spi_read()
310 .tx_buf = st->tx_data, in ad4030_spi_write()
315 if (count > sizeof(st->tx_data)) in ad4030_spi_write()
316 return -EINVAL; in ad4030_spi_write()
322 memcpy(st->tx_data, data, count); in ad4030_spi_write()
324 ret = spi_sync_transfer(st->spi, &xfer, 1); in ad4030_spi_write()
331 * After a reset we are in conversion mode, no need to exit config mode in ad4030_spi_write()
388 scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels); in ad4030_get_chan_scale()
392 if (chan->differential) in ad4030_get_chan_scale()
393 *val = (st->vref_uv * 2) / MILLI; in ad4030_get_chan_scale()
395 *val = st->vref_uv / MILLI; in ad4030_get_chan_scale()
397 *val2 = scan_type->realbits; in ad4030_get_chan_scale()
411 ret = regmap_bulk_read(st->regmap, AD4030_REG_GAIN_CHAN(chan->address), in ad4030_get_chan_calibscale()
412 st->rx_data.raw, AD4030_REG_GAIN_BYTES_NB); in ad4030_get_chan_calibscale()
416 gain = get_unaligned_be16(st->rx_data.raw); in ad4030_get_chan_calibscale()
426 /* Returns the offset where 1 LSB = (VREF/2^precision_bits - 1)/gain */
434 ret = regmap_bulk_read(st->regmap, in ad4030_get_chan_calibbias()
435 AD4030_REG_OFFSET_CHAN(chan->address), in ad4030_get_chan_calibbias()
436 st->rx_data.raw, AD4030_REG_OFFSET_BYTES_NB); in ad4030_get_chan_calibbias()
440 switch (st->chip->precision_bits) { in ad4030_get_chan_calibbias()
442 *val = sign_extend32(get_unaligned_be16(st->rx_data.raw), 15); in ad4030_get_chan_calibbias()
446 *val = sign_extend32(get_unaligned_be24(st->rx_data.raw), 23); in ad4030_get_chan_calibbias()
450 return -EINVAL; in ad4030_get_chan_calibbias()
463 return -EINVAL; in ad4030_set_chan_calibscale()
468 return -EINVAL; in ad4030_set_chan_calibscale()
472 st->tx_data); in ad4030_set_chan_calibscale()
474 return regmap_bulk_write(st->regmap, in ad4030_set_chan_calibscale()
475 AD4030_REG_GAIN_CHAN(chan->address), in ad4030_set_chan_calibscale()
476 st->tx_data, AD4030_REG_GAIN_BYTES_NB); in ad4030_set_chan_calibscale()
485 if (offset < st->offset_avail[0] || offset > st->offset_avail[2]) in ad4030_set_chan_calibbias()
486 return -EINVAL; in ad4030_set_chan_calibbias()
488 st->tx_data[2] = 0; in ad4030_set_chan_calibbias()
490 switch (st->chip->precision_bits) { in ad4030_set_chan_calibbias()
492 put_unaligned_be16(offset, st->tx_data); in ad4030_set_chan_calibbias()
496 put_unaligned_be24(offset, st->tx_data); in ad4030_set_chan_calibbias()
500 return -EINVAL; in ad4030_set_chan_calibbias()
503 return regmap_bulk_write(st->regmap, in ad4030_set_chan_calibbias()
504 AD4030_REG_OFFSET_CHAN(chan->address), in ad4030_set_chan_calibbias()
505 st->tx_data, AD4030_REG_OFFSET_BYTES_NB); in ad4030_set_chan_calibbias()
512 unsigned int last_avg_idx = ARRAY_SIZE(ad4030_average_modes) - 1; in ad4030_set_avg_frame_len()
516 return -EINVAL; in ad4030_set_avg_frame_len()
518 ret = regmap_write(st->regmap, AD4030_REG_AVG, in ad4030_set_avg_frame_len()
524 st->avg_log2 = avg_log2; in ad4030_set_avg_frame_len()
532 return mask & (st->chip->num_voltage_inputs == 1 ? in ad4030_is_common_byte_asked()
541 if (st->avg_log2 > 0) { in ad4030_set_mode()
542 st->mode = AD4030_OUT_DATA_MD_30_AVERAGED_DIFF; in ad4030_set_mode()
544 switch (st->chip->precision_bits) { in ad4030_set_mode()
546 st->mode = AD4030_OUT_DATA_MD_16_DIFF_8_COM; in ad4030_set_mode()
550 st->mode = AD4030_OUT_DATA_MD_24_DIFF_8_COM; in ad4030_set_mode()
554 return -EINVAL; in ad4030_set_mode()
557 st->mode = AD4030_OUT_DATA_MD_DIFF; in ad4030_set_mode()
560 return regmap_update_bits(st->regmap, AD4030_REG_MODES, in ad4030_set_mode()
562 st->mode); in ad4030_set_mode()
610 unsigned long cnv_nb = BIT(st->avg_log2); in ad4030_conversion()
614 scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels); in ad4030_conversion()
618 diff_realbytes = BITS_TO_BYTES(scan_type->realbits); in ad4030_conversion()
619 diff_storagebytes = BITS_TO_BYTES(scan_type->storagebits); in ad4030_conversion()
621 /* Number of bytes for one differential channel */ in ad4030_conversion()
623 /* Add one byte if we are using a differential + common byte mode */ in ad4030_conversion()
624 bytes_to_read += (st->mode == AD4030_OUT_DATA_MD_24_DIFF_8_COM || in ad4030_conversion()
625 st->mode == AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0; in ad4030_conversion()
627 bytes_to_read *= st->chip->num_voltage_inputs; in ad4030_conversion()
630 gpiod_set_value_cansleep(st->cnv_gpio, 1); in ad4030_conversion()
632 gpiod_set_value_cansleep(st->cnv_gpio, 0); in ad4030_conversion()
633 ndelay(st->chip->tcyc_ns); in ad4030_conversion()
636 ret = spi_read(st->spi, st->rx_data.raw, bytes_to_read); in ad4030_conversion()
640 if (st->chip->num_voltage_inputs == 2) in ad4030_conversion()
641 ad4030_extract_interleaved(st->rx_data.raw, in ad4030_conversion()
642 &st->rx_data.dual.diff[0], in ad4030_conversion()
643 &st->rx_data.dual.diff[1]); in ad4030_conversion()
646 * If no common mode voltage channel is enabled, we can use the raw in ad4030_conversion()
651 if (st->mode != AD4030_OUT_DATA_MD_16_DIFF_8_COM && in ad4030_conversion()
652 st->mode != AD4030_OUT_DATA_MD_24_DIFF_8_COM) in ad4030_conversion()
655 if (st->chip->num_voltage_inputs == 1) { in ad4030_conversion()
656 st->rx_data.single.common = st->rx_data.raw[diff_realbytes]; in ad4030_conversion()
660 for (i = 0; i < st->chip->num_voltage_inputs; i++) in ad4030_conversion()
661 st->rx_data.dual.common[i] = in ad4030_conversion()
662 st->rx_data.raw[diff_storagebytes * i + diff_realbytes]; in ad4030_conversion()
673 ret = ad4030_set_mode(indio_dev, BIT(chan->scan_index)); in ad4030_single_conversion()
681 if (chan->differential) in ad4030_single_conversion()
682 if (st->chip->num_voltage_inputs == 1) in ad4030_single_conversion()
683 *val = st->rx_data.single.diff; in ad4030_single_conversion()
685 *val = st->rx_data.dual.diff[chan->address]; in ad4030_single_conversion()
687 if (st->chip->num_voltage_inputs == 1) in ad4030_single_conversion()
688 *val = st->rx_data.single.common; in ad4030_single_conversion()
690 *val = st->rx_data.dual.common[chan->address]; in ad4030_single_conversion()
698 struct iio_dev *indio_dev = pf->indio_dev; in ad4030_trigger_handler()
706 iio_push_to_buffers_with_ts(indio_dev, &st->rx_data, sizeof(st->rx_data), in ad4030_trigger_handler()
707 pf->timestamp); in ad4030_trigger_handler()
710 iio_trigger_notify_done(indio_dev->trig); in ad4030_trigger_handler()
722 struct iio_chan_spec const *channel, in ad4030_read_avail() argument
730 *vals = st->offset_avail; in ad4030_read_avail()
746 return -EINVAL; in ad4030_read_avail()
767 *val = BIT(st->avg_log2); in ad4030_read_raw_dispatch()
771 return -EINVAL; in ad4030_read_raw_dispatch()
785 return -EBUSY; in ad4030_read_raw()
804 return -EINVAL; in ad4030_write_raw_dispatch()
811 return -EINVAL; in ad4030_write_raw_dispatch()
822 return -EBUSY; in ad4030_write_raw()
838 return -EBUSY; in ad4030_reg_access()
841 ret = regmap_read(st->regmap, reg, readval); in ad4030_reg_access()
843 ret = regmap_write(st->regmap, reg, writeval); in ad4030_reg_access()
854 if (chan->differential) in ad4030_read_label()
855 return sprintf(label, "differential%lu\n", chan->address); in ad4030_read_label()
856 return sprintf(label, "common-mode%lu\n", chan->address); in ad4030_read_label()
864 return st->avg_log2 ? AD4030_SCAN_TYPE_AVG : AD4030_SCAN_TYPE_NORMAL; in ad4030_get_current_scan_type()
888 /* Asking for both common channels and averaging */ in ad4030_validate_scan_mask()
889 if (st->avg_log2 && ad4030_is_common_byte_asked(st, *scan_mask)) in ad4030_validate_scan_mask()
901 struct device *dev = &st->spi->dev; in ad4030_regulators_get()
902 static const char * const ids[] = { "vdd-5v", "vdd-1v8" }; in ad4030_regulators_get()
909 st->vio_uv = devm_regulator_get_enable_read_voltage(dev, "vio"); in ad4030_regulators_get()
910 if (st->vio_uv < 0) in ad4030_regulators_get()
911 return dev_err_probe(dev, st->vio_uv, in ad4030_regulators_get()
914 st->vref_uv = devm_regulator_get_enable_read_voltage(dev, "ref"); in ad4030_regulators_get()
915 if (st->vref_uv < 0) { in ad4030_regulators_get()
916 if (st->vref_uv != -ENODEV) in ad4030_regulators_get()
917 return dev_err_probe(dev, st->vref_uv, in ad4030_regulators_get()
921 st->vref_uv = devm_regulator_get_enable_read_voltage(dev, in ad4030_regulators_get()
923 if (st->vref_uv < 0) in ad4030_regulators_get()
924 return dev_err_probe(dev, st->vref_uv, in ad4030_regulators_get()
933 struct device *dev = &st->spi->dev; in ad4030_reset()
947 return regmap_write(st->regmap, AD4030_REG_INTERFACE_CONFIG_A, in ad4030_reset()
956 ret = regmap_read(st->regmap, AD4030_REG_CHIP_GRADE, &grade); in ad4030_detect_chip_info()
961 if (grade != st->chip->grade) in ad4030_detect_chip_info()
962 dev_warn(&st->spi->dev, "Unknown grade(0x%x) for %s\n", grade, in ad4030_detect_chip_info()
963 st->chip->name); in ad4030_detect_chip_info()
973 st->offset_avail[0] = (int)BIT(st->chip->precision_bits - 1) * -1; in ad4030_config()
974 st->offset_avail[1] = 1; in ad4030_config()
975 st->offset_avail[2] = BIT(st->chip->precision_bits - 1) - 1; in ad4030_config()
977 if (st->chip->num_voltage_inputs > 1) in ad4030_config()
984 ret = regmap_write(st->regmap, AD4030_REG_MODES, reg_modes); in ad4030_config()
988 if (st->vio_uv < AD4030_VIO_THRESHOLD_UV) in ad4030_config()
989 return regmap_write(st->regmap, AD4030_REG_IO, in ad4030_config()
997 struct device *dev = &spi->dev; in ad4030_probe()
1004 return -ENOMEM; in ad4030_probe()
1007 st->spi = spi; in ad4030_probe()
1009 st->regmap = devm_regmap_init(dev, &ad4030_regmap_bus, st, in ad4030_probe()
1011 if (IS_ERR(st->regmap)) in ad4030_probe()
1012 return dev_err_probe(dev, PTR_ERR(st->regmap), in ad4030_probe()
1015 st->chip = spi_get_device_match_data(spi); in ad4030_probe()
1016 if (!st->chip) in ad4030_probe()
1017 return -EINVAL; in ad4030_probe()
1041 st->cnv_gpio = devm_gpiod_get(dev, "cnv", GPIOD_OUT_LOW); in ad4030_probe()
1042 if (IS_ERR(st->cnv_gpio)) in ad4030_probe()
1043 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), in ad4030_probe()
1047 * One hardware channel is split in two software channels when using in ad4030_probe()
1048 * common byte mode. Add one more channel for the timestamp. in ad4030_probe()
1050 indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1; in ad4030_probe()
1051 indio_dev->name = st->chip->name; in ad4030_probe()
1052 indio_dev->modes = INDIO_DIRECT_MODE; in ad4030_probe()
1053 indio_dev->info = &ad4030_iio_info; in ad4030_probe()
1054 indio_dev->channels = st->chip->channels; in ad4030_probe()
1055 indio_dev->available_scan_masks = st->chip->available_masks; in ad4030_probe()
1071 /* Differential and common-mode voltage */
1079 /* Differential with common byte */
1119 .name = "ad4030-24",
1133 .name = "ad4630-16",
1149 .name = "ad4630-24",
1165 .name = "ad4632-16",
1181 .name = "ad4632-24",
1197 { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info },
1198 { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info },
1199 { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info },
1200 { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info },
1201 { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info },
1207 { .compatible = "adi,ad4030-24", .data = &ad4030_24_chip_info },
1208 { .compatible = "adi,ad4630-16", .data = &ad4630_16_chip_info },
1209 { .compatible = "adi,ad4630-24", .data = &ad4630_24_chip_info },
1210 { .compatible = "adi,ad4632-16", .data = &ad4632_16_chip_info },
1211 { .compatible = "adi,ad4632-24", .data = &ad4632_24_chip_info },