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Searched +full:cmn +full:- +full:600 (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Darm,cmn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/perf/arm,cmn.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Arm CMN (Coherent Mesh Network) Performance Monitors
11 - Robin Murphy <robin.murphy@arm.com>
16 - arm,cmn-600
17 - arm,cmn-650
18 - arm,cmn-700
19 - arm,ci-700
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/freebsd/lib/libpmc/
H A Dpmc.cmn-600.328 .Nm pmc.cmn-600
29 .Nd Library for accessing the Arm CoreLink CMN-600 Coherent Mesh Network
36 CMN-600 PMU counters may be configured to count any one of a defined set of
38 Unlike other performance counters, counters for the CMN-600 require the
52 Some BIOS versions of dual-socket machines have no NUMA domain information in
57 the CPU package containing that CMN-600 controller.
64 Arm CoreLink CMN-600 Coherent Mesh Network Controller performance counters are
67 .%B "Arm CoreLink CMN-600 Coherent Mesh Network Technical Reference Manual"
73 CMN-600 PMU counters support the following capabilities:
74 .Bl -column "PMC_CAP_INTERRUPT" "Support"
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/freebsd/sys/arm64/include/
H A Dpmc_mdep.h1 /*-
37 * ARMV8 ARM Cortex-A53/57/72 processors
68 #define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_elr)
69 #define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_x[29])
77 /* Optional class for CMN-600 controler's PMU. */
82 /* Optional class for DMC-620 controler's PMU. */
/freebsd/sys/arm64/arm64/
H A Dcmn600.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
28 /* Arm CoreLink CMN-600 Coherent Mesh Network Driver */
51 #define RD4(sc, r) bus_read_4((sc)->sc_res[0], (r))
52 #define RD8(sc, r) bus_read_8((sc)->sc_res[0], (r))
53 #define WR4(sc, r, v) bus_write_4((sc)->sc_res[0], (r), (v))
54 #define WR8(sc, r, v) bus_write_8((sc)->sc_res[0], (r), (v))
66 { -1, 0 }
136 cmn600_npmcs--; in cmn600_pmc_unregister()
165 switch (sc->sc_rev) { in pmu_cmn600_rev()
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/freebsd/sys/dev/hwpmc/
H A Dhwpmc_cmn600.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2003-2008 Joseph Koshy
33 /* Arm CoreLink CMN-600 Coherent Mesh Network PMU Driver */
149 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, in cmn600_read_pmc()
154 arg = desc->pd_rw_arg; in cmn600_read_pmc()
155 nodeid = pm->pm_md.pm_cmn600.pm_cmn600_nodeid; in cmn600_read_pmc()
156 local_counter = pm->pm_md.pm_cmn600.pm_cmn600_local_counter; in cmn600_read_pmc()
159 PMCDBG3(MDP, REA, 2, "%s id=%d -> %jd", __func__, ri, *v); in cmn600_read_pmc()
176 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, in cmn600_write_pmc()
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H A Dpmc_events.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 * __PMC_EV(CLASS, SYMBOLIC-NAME)
63 #define PMC_EV_SOFT_LAST (PMC_EV_SOFT_FIRST + PMC_EV_DYN_COUNT - 1)
154 * from the "Intel 64 and IA-32 Architectures Software Developer's
166 __PMC_EV_ALIAS("instruction-retired", IAF_INSTR_RETIRED_ANY) \
167 __PMC_EV_ALIAS("unhalted-core-cycles", IAF_CPU_CLK_UNHALTED_CORE) \
168 __PMC_EV_ALIAS("unhalted-reference-cycles", IAF_CPU_CLK_UNHALTED_REF)
551 * NB: ARMv8.1 extends this to a 16-bit encoding, but we only define the 10-bit
1716 * ARM DMC-620 memory controller counters.
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/freebsd/contrib/one-true-awk/testdir/
H A Dfunstack.in2 %%% BibTeX-file{
23 %%% (incompletely) 1970 -- 1979.
50 %%% covering 1958--1996 became too large (about
65 %%% Algorithms 1--492. For Algorithms 493--686,
72 %%% cross-referenced in both directions, so
75 %%% Corrigenda. Cross-referenced entries are
77 %%% that each is completely self-contained.
83 %%% ftp://netlib.bell-labs.com/netlib/toms.
88 %%% http://ciir.cs.umass.edu/cgi-bin/web_query_form/public/cacm2.1.
90 %%% The initial draft of entries for 1981 --
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