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/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
26 sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
[all …]
H A Dam33xx-clocks.dtsi3 * Device Tree Source for AM33xx clock data
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
22 clock-mult = <1>;
[all …]
H A Domap3xxx-clocks.dtsi3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
32 #clock-cells = <0>;
33 compatible = "ti,gate-clock";
[all …]
H A Domap54xx-clocks.dtsi3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
H A Domap44xx-clocks.dtsi3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap24xx-clocks.dtsi3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
39 #clock-cells = <0>;
[all …]
H A Ddm814x-clocks.dtsi10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
34 compatible = "ti,dm814-adpll-lj-clock";
[all …]
H A Domap34xx-omap36xx-clocks.dtsi3 * Device Tree Source for OMAP34XX/OMAP36XX clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
16 clock@a14 {
19 #clock-cells = <2>;
23 aes1_ick: clock-aes1-ick@3 {
25 #clock-cells = <0>;
26 compatible = "ti,omap3-interface-clock";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
24 clock@a40 {
27 #clock-cells = <2>;
31 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 {
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
26 #clock-cells = <0>;
[all …]
H A Domap3430es1-clocks.dtsi3 * Device Tree Source for OMAP3430 ES1 clock data
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
26 #clock-cells = <0>;
27 compatible = "fixed-factor-clock";
29 clock-mult = <1>;
30 clock-div = <1>;
34 #clock-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi3 * Device Tree Source for Keystone 2 clock tree
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
20 clock-output-names = "mainmuxclk";
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
27 clock-div = <1>;
28 clock-mult = <1>;
29 clock-output-names = "chipclk1";
33 #clock-cells = <0>;
[all …]
H A Dkeystone-k2hk-clocks.dtsi3 * Keystone 2 Kepler/Hawking SoC clock nodes
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
27 #clock-cells = <0>;
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "papllclk";
36 #clock-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi41 clock-names = "timclk", "apb_pclk";
50 clock-names = "timclk", "apb_pclk";
199 #clock-cells = <0>;
200 compatible = "fixed-clock";
201 clock-frequency = <19200000>;
205 * The 2.4 MHz TIMCLK reference clock is active at
207 * divided by 8. This clock is used by the timers and
211 #clock-cells = <0>;
212 compatible = "fixed-factor-clock";
213 clock-div = <8>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5260-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
7 title: Samsung Exynos5260 SoC clock controller
18 - "fin_pll" - PLL input clock from XXTI
19 - "xrtcxti" - input clock from XRTCXTI
20 - "ioclk_pcm_extclk" - pcm external operation clock
21 - "ioclk_spdif_extclk" - spdif external operation clock
22 - "ioclk_i2s_cdclk" - i2s0 codec clock
26 are fed into the clock controller and then routed to the hardware blocks.
28 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
29 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
[all …]
H A Dst,stm32mp25-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
7 title: STM32MP25 Reset Clock Controller
13 The RCC hardware block is both a reset and a clock controller.
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
28 '#clock-cells':
42 - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
43 - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
44 - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
45 - description: CK_SCMI_ICN_DDR DDR interconnect bus clock
46 - description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
[all …]
H A Dtesla,fsd-clock.yaml4 $id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
7 title: Tesla FSD (Full Self-Driving) SoC clock controller
14 FSD clock controller consist of several clock management unit
16 The root clock comes from external OSC clock (24 MHz).
19 'dt-bindings/clock/fsd-clk.h' header.
24 - tesla,fsd-clock-cmu
25 - tesla,fsd-clock-imem
26 - tesla,fsd-clock-peric
27 - tesla,fsd-clock-fsys0
28 - tesla,fsd-clock-fsys1
[all …]
H A Dsamsung,exynos850-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
7 title: Samsung Exynos850 SoC clock controller
17 Exynos850 clock controller is comprised of several CMU units, generating
19 tree nodes, and might depend on each other. Root clocks in that clock tree are
26 Each clock is assigned an identifier and client nodes can use this identifier
27 to specify the clock which they consume. All clocks available for usage
28 in clock consumer nodes are defined as preprocessor macros in
29 'dt-bindings/clock/exynos850.h' header.
52 clock-names:
56 "#clock-cells":
[all …]
H A Dsamsung,exynos8895-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
7 title: Samsung Exynos8895 SoC clock controller
15 Exynos8895 clock controller is comprised of several CMU units, generating
17 tree nodes, and might depend on each other. The root clock in that root tree
18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
19 as a fixed-rate clock in dts.
25 Each clock is assigned an identifier and client nodes can use this identifier
26 to specify the clock which they consume. All clocks available for usage
27 in clock consumer nodes are defined as preprocessor macros in
28 'include/dt-bindings/clock/samsung,exynos8895.h' header.
[all …]
H A Dsocionext,uniphier-clock.yaml4 $id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
7 title: UniPhier clock controller
15 - description: System clock
17 - socionext,uniphier-ld4-clock
18 - socionext,uniphier-pro4-clock
19 - socionext,uniphier-sld8-clock
20 - socionext,uniphier-pro5-clock
21 - socionext,uniphier-pxs2-clock
22 - socionext,uniphier-ld6b-clock
23 - socionext,uniphier-ld11-clock
[all …]
H A Dsamsung,exynos7-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
7 title: Samsung Exynos7 SoC clock controller
18 - "fin_pll" - PLL input clock from XXTI
21 include/dt-bindings/clock/exynos7-clk.h header.
26 - samsung,exynos7-clock-topc
27 - samsung,exynos7-clock-top0
28 - samsung,exynos7-clock-top1
29 - samsung,exynos7-clock-ccore
30 - samsung,exynos7-clock-peric0
31 - samsung,exynos7-clock-peric1
[all …]
/linux/drivers/clk/mediatek/
H A DKconfig3 # MediaTek Clock Drivers
5 menu "Clock driver for MediaTek SoC"
12 MediaTek SoCs' clock support.
15 bool "clock driver for MediaTek FHCTL hardware control"
22 bool "Clock driver for MediaTek MT2701"
30 bool "Clock driver for MediaTek MT2701 mmsys"
36 bool "Clock driver for MediaTek MT2701 imgsys"
42 bool "Clock driver for MediaTek MT2701 vdecsys"
48 bool "Clock driver for MediaTek MT2701 hifsys"
54 bool "Clock driver for MediaTek MT2701 ethsys"
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
39 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
40 clock-names = "bus";
46 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
47 clock-names = "bus";
53 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
54 clock-names = "bus";
60 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
61 clock-names = "bus";
[all …]
H A Dexynos5410.dtsi14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
37 clock-frequency = <1600000000>;
44 clock-frequency = <1600000000>;
51 clock-frequency = <1600000000>;
58 clock-frequency = <1600000000>;
71 clock-names = "clkout16";
73 #clock-cells = <1>;
76 clock: clock-controller@10010000 { label
77 compatible = "samsung,exynos5410-clock";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-audio.dtsi7 #include <dt-bindings/clock/imx8-clock.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
12 audio_ipg_clk: clock-audio-ipg {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <120000000>;
16 clock-output-names = "audio_ipg_clk";
19 clk_ext_aud_mclk0: clock-ext-aud-mclk0 {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
[all …]

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