| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | ti-aemif.txt | 1 * Device tree bindings for Texas instruments AEMIF controller
4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
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| H A D | arm,pl172.txt | 1 * Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller
5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | dw_hdmi.txt | 4 This document defines device tree properties for the Synopsys DesignWare HDMI
5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
6 specification by itself but is meant to be referenced by platform-specific
7 device tree bindings.
9 When referenced from platform device tree bindings the properties defined in
10 this document are defined as follows. The platform device tree bindings are
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
15 - reg-io-width: Width of the registers specified by the reg property. The
19 - interrupts: Reference to the DWC HDMI TX interrupt.
21 - clocks: References to all the clocks specified in the clock-names property
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| H A D | synopsys,dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This document defines device tree properties for the Synopsys DesignWare HDMI
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
15 binding specification by itself but is meant to be referenced by device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
18 When referenced from platform device tree bindings the properties defined in
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| H A D | toshiba,tc358767.txt | 4 - compatible: "toshiba,tc358767"
5 - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
6 - clock-names: should be "ref"
7 - clocks: OF device-tree clock specification for refclk input. The reference
8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
11 - shutdown-gpios: OF device-tree gpio specification for SD pin
13 - reset-gpios: OF device-tree gpio specification for RSTX pin
15 - toshiba,hpd-pin: TC358767 GPIO pin number to which HPD is connected to (0 or 1)
16 - ports: the ports node can contain video interface port nodes to connect
18 - port@0: DSI input port
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/ |
| H A D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
16 Since the clock instances are part of a single IP this binding is used as a node
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | renesas,emev2-smu.txt | 1 Device tree Clock bindings for Renesas EMMA Mobile EV2
3 This binding uses the common clock binding.
7 This is not a clock provider, but clocks under SMU depend on it.
10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
15 "Serial clock generator" in fig."Clock System Overview" of the manual,
17 This makes internal (neither input nor output) clock that is provided
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
22 - reg: Byte offset from SMU base and Bit position in the register
23 - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
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| H A D | exynos7-clock.txt | 1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
12 device tree sources.
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
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| H A D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
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| H A D | amlogic,meson8b-clkc.txt | 1 * Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
3 The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
4 supplies clock to various controllers within the SoC.
8 - compatible: must be one of:
9 - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
10 - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
11 - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
14 - clocks: list of clock phandles, one for each entry in clock-names
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| H A D | rockchip,rk3288-cru.txt | 1 * Rockchip RK3288 Clock and Reset Unit
3 The RK3288 clock controller generates and supplies clock to various
7 A revision of this SoC is available: rk3288w. The clock tree is a bit
8 different so another dt-compatible is available. Noticed that it is only
14 - compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
16 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
19 - #reset-cells: should be 1.
23 - rockchip,grf: phandle to the syscon managing the "general register files"
26 Each clock is assigned an identifier and client nodes can use this identifier
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| H A D | xlnx,zynqmp-clk.txt | 1 --------------------------------------------------------------------------
2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
4 --------------------------------------------------------------------------
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
6 tree. It reads required input clock frequencies from the devicetree and acts
7 as clock provider for all clock consumers of PS clocks.
9 See clock_bindings.txt for more information on the generic clock bindings.
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
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| H A D | rockchip,rk3288-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3288 Clock and Reset Unit (CRU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3288 clock controller generates and supplies clocks to various
18 A revision of this SoC is available: rk3288w. The clock tree is a bit
19 different so another dt-compatible is available. Noticed that it is only
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| H A D | st,nomadik.txt | 3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 PLLs and clock gates.
10 - compatible: must be "stericsson,nomadik-src"
11 - reg: must contain the SRC register base and size
14 - disable-sxtalo: if present this will disable the SXTALO
17 - disable-mxtal: if present this will disable the MXTALO,
25 fixed frequency clock, as parent.
28 - compatible: must be "st,nomadik-pll-clock"
29 - clock-cells: must be 0
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| H A D | amlogic,gxbb-aoclkc.txt | 1 * Amlogic GXBB AO Clock and Reset Unit
3 The Amlogic GXBB AO clock controller generates and supplies clock to various
4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
14 followed by the common "amlogic,meson-gx-aoclkc"
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| H A D | samsung,s2mps11.txt | 1 Binding for Samsung S2M and S5M family clock generator block
4 This is a part of device tree bindings for S2M and S5M family multi-function
6 More information can be found in bindings/mfd/sec-core.txt file.
11 To register these as clocks with common clock framework instantiate under
12 main device node a sub-node named "clocks".
14 It uses the common clock binding documented in:
15 - Documentation/devicetree/bindings/clock/clock-bindings.txt
18 Required properties of the "clocks" sub-node:
19 - #clock-cells: should be 1.
20 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk",
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| H A D | zynq-7000.txt | 1 Device Tree Clock bindings for the Zynq 7000 EPP
6 See clock_bindings.txt for more information on the generic clock bindings.
9 == Clock Controller ==
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
11 required input clock frequencies from the devicetree and acts as clock provider
12 for all clock consumers of PS clocks.
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
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| H A D | renesas,emev2-smu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
24 '#address-cells':
27 '#size-cells':
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_spi.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
58 {"broadcom,bcm2835-spi", 1},
59 {"brcm,bcm2835-spi", 1},
81 reg--; in bcm_spi_printr()
105 mtx_assert(&sc->sc_mtx, MA_OWNED); in bcm_spi_modifyreg()
130 if (error != 0 || req->newptr == NULL) in bcm_spi_clock_proc()
150 if (error != 0 || req->newptr == NULL) in bcm_spi_cs_bit_proc()
196 struct sysctl_oid_list *tree; in bcm_spi_sysctl_init() local
199 * Add system sysctl tree/handlers. in bcm_spi_sysctl_init()
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| /freebsd/sys/contrib/device-tree/Bindings/clock/sifive/ |
| H A D | fu540-prci.txt | 3 On the FU540 family of SoCs, most system-wide clock and reset integration
7 - compatible: Should be "sifive,<chip>-prci". Only one value is
8 supported: "sifive,fu540-c000-prci"
9 - reg: Should describe the PRCI's register target physical address region
10 - clocks: Should point to the hfclk device tree node and the rtcclk
11 device tree node. The RTC clock here is not a time-of-day clock,
12 but is instead a high-stability clock source for system timers
14 - #clock-cells: Should be <1>
16 The clock consumer should specify the desired clock via the clock ID
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | brcm,bcm2835-unicam.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/brcm,bcm2835-unicam.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
12 description: |-
14 CSI-2 or CCP2 data from image sensors or similar devices.
19 the firmware checks the device tree configuration during boot. If it finds
20 device tree nodes whose name starts with 'csi' then it will stop the firmware
21 accessing the block, and it can then safely be used via the device tree
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| /freebsd/usr.bin/dtc/ |
| H A D | dtc.cc | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
72 "\t%s\t[-fhsv@] [-b boot_cpu_id] [-d dependency_file]" in usage()
73 "[-E [no-]checker_name]\n" in usage()
74 "\t\t[-H phandle_format] [-I input_format]" in usage()
75 "[-O output_format]\n" in usage()
76 "\t\t[-o output_file] [-R entries] [-S bytes] [-p bytes]" in usage()
77 "[-V blob_version]\n" in usage()
78 "\t\t-W [no-]checker_name] input_file\n", basename(argv0).c_str()); in usage()
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | dsi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 This document defines device tree properties common to DSI, Display
15 a device tree binding specification by itself but is meant to be referenced
16 by device tree bindings.
18 When referenced from panel device tree bindings the properties defined in
19 this document are defined as follows. The panel device tree bindings are
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | fsl-flexcan.txt | 1 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
5 - compatible : Should be "fsl,<processor>-flexcan"
10 - fsl,p1010-flexcan
12 - reg : Offset and length of the register set for this device
13 - interrupts : Interrupt tuple for this device
17 - clock-frequency : The oscillator frequency driving the flexcan device
19 - xceiver-supply: Regulator that powers the CAN transceiver
21 - big-endian: This means the registers of FlexCAN controller are big endian.
23 device tree node then controller is assumed to be little endian.
27 - fsl,stop-mode: register bits of stop mode control, the format is
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| /freebsd/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | pwm-fsl-ftm.txt | 4 device tree provides a property to describing this so that an operating system
8 SoC | FTM-PWM endianness
9 --------+-------------------
15 modes in device tree.
19 - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
21 - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23 - reg: Physical base address and length of the controller's registers
24 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
26 - clock-names: Should include the following module clock source entries:
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