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/freebsd/sys/contrib/device-tree/Bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera SOCFPGA Clock Manager
10 - Dinh Nguyen <dinguyen@kernel.org>
13 This binding describes the Altera SOCFGPA Clock Manager and its associated
14 tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
20 - const: altr,clk-mgr
30 "#address-cells":
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmc-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
12 specific like delay in clock or data lines, etc. These properties need
13 to be defined in the peripheral node because they are per-peripheral
20 - Marek Vasut <marex@denx.de>
26 bank-width:
32 - reg
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dfsl,dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,dspi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for Freescale DSPI controller
10 - Vladimir Oltean <olteanv@gmail.com>
13 See spi-peripheral-props.yaml for more info.
16 fsl,spi-cs-sck-delay:
20 clock signal, at the start of a transfer.
23 fsl,spi-sck-cs-delay:
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H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
12 be controller specific like delay in clock or data lines, etc. These
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
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H A Dcdns,qspi-nor-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
20 Delay for read capture logic, in clock cycles.
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H A Dnvidia,tegra210-quad-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 nvidia,tx-clk-tap-delay:
16 Delays the clock going out to device with this tap value.
23 nvidia,rx-clk-tap-delay:
25 Delays the clock coming in from the device with this tap value.
/freebsd/sys/dev/mmc/
H A Dmmc_helpers.c44 * All UHS-I modes requires 1.8V signaling. in mmc_parse_sd_speed()
46 if (device_has_property(dev, "no-1-8-v")) in mmc_parse_sd_speed()
48 if (device_has_property(dev, "cap-sd-highspeed")) in mmc_parse_sd_speed()
49 host->caps |= MMC_CAP_HSPEED; in mmc_parse_sd_speed()
50 if (device_has_property(dev, "sd-uhs-sdr12") && !no_18v) in mmc_parse_sd_speed()
51 host->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_SIGNALING_180; in mmc_parse_sd_speed()
52 if (device_has_property(dev, "sd-uhs-sdr25") && !no_18v) in mmc_parse_sd_speed()
53 host->caps |= MMC_CAP_UHS_SDR25 | MMC_CAP_SIGNALING_180; in mmc_parse_sd_speed()
54 if (device_has_property(dev, "sd-uhs-sdr50") && !no_18v) in mmc_parse_sd_speed()
55 host->caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_SIGNALING_180; in mmc_parse_sd_speed()
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/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4371.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Popa Stefan <stefan.popa@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf
20 - adi,adf4371
21 - adi,adf4372
28 Definition of the external clock (see clock/clock-bindings.txt)
31 clock-names:
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H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dadi,adf4377.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
11 - Dragos Bogdan <dragos.bogdan@analog.com>
14 The ADF4377 is a high performance, ultralow jitter, dual output integer-N
16 ideally suited for data converter and mixed signal front end (MxFE) clock
25 - adi,adf4377
26 - adi,adf4378
31 spi-max-frequency:
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H A Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
36 - const: lo_in
38 clock-output-names:
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H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dnxp,pcf85063.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP PCF85063 Real Time Clock
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - microcrystal,rv8063
16 - microcrystal,rv8263
17 - nxp,pcf85063
18 - nxp,pcf85063a
19 - nxp,pcf85063tp
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
6 See clock_bindings.txt for more information on the generic clock bindings.
9 == Clock Controller ==
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
11 required input clock frequencies from the devicetree and acts as clock provider
12 for all clock consumers of PS clocks.
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dfairchild,74hc595.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
11 have a rising-edge triggered latch clock (or storage register clock) pin,
12 which behaves like an active-low chip select.
15 the 74HC595 sees as a rising edge on the latch clock that results in a
19 shift clock ____| |_| |_..._| |_| |_________
21 latch clock * trigger
27 - Maxime Ripard <mripard@kernel.org>
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/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dti,wlcore.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 Note that the *-clock-frequency properties assume internal clocks. In case
15 of external clocks, new bindings (for parsing the clock nodes) have to be
21 - ti,wl1271
22 - ti,wl1273
23 - ti,wl1281
24 - ti,wl1283
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H A Dmicrochip,wilc1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adham Abozaeid <adham.abozaeid@microchip.com>
11 - Ajay Singh <ajay.kathat@microchip.com>
20 - items:
21 - const: microchip,wilc3000
22 - const: microchip,wilc1000
23 - const: microchip,wilc1000
31 description: phandle to the clock connected on rtc clock line.
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Drealtek,rt5514.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
24 - $ref: /schemas/spi/spi-peripheral-props.yaml#
25 - $ref: dai-common.yaml#
36 - description: Master clock to the CODEC
38 clock-names:
40 - const: mclk
46 realtek,dmic-init-delay-ms:
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H A Dinfineon,peb2466.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
13 The Infineon PEB2466 codec is a programmable DSP-based four channels codec
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the sound card node for sub-nodes
19 that involve the codec. The codec uses one 8bit time-slot per channel.
20 'dai-tdm-tdm-slot-with' must be set to 8.
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/freebsd/sys/contrib/device-tree/Bindings/iio/imu/
H A Dadi,adis16480.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - enum:
16 - adi,adis16375
17 - adi,adis16480
18 - adi,adis16485
19 - adi,adis16486
20 - adi,adis16488
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dadi,ad4080.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Analog Devices AD4080 20-Bit, 40 MSPS, Differential SAR ADC
11 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 The AD4080 is a high speed, low noise, low distortion, 20-bit, Easy Drive,
15 successive approximation register (SAR) analog-to-digital converter (ADC).
16 Maintaining high performance (signal-to-noise and distortion (SINAD) ratio
21 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4080.pdf
23 $ref: /schemas/spi/spi-peripheral-props.yaml#
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dsamsung,s5c73m3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 The S5C73M3 camera ISP supports MIPI CSI-2 and parallel (ITU-R BT.656)
31 clock-names:
33 - const: cis_extclk
35 clock-frequency:
37 description: cis_extclk clock frequency.
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/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dnxp,sc16is7xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP SC16IS7xx Advanced Universal Asynchronous Receiver-Transmitter (UART)
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
15 - nxp,sc16is740
16 - nxp,sc16is741
17 - nxp,sc16is750
18 - nxp,sc16is752
19 - nxp,sc16is760
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmaxim,ds26522.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - const: maxim,ds26522
21 - compatible
22 - reg
25 - $ref: /schemas/spi/spi-peripheral-props.yaml
30 - |
32 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/net/bluetooth/
H A Dti,bluetooth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Lechner <david@lechnology.com>
32 - ti,cc2560
33 - ti,wl1271-st
34 - ti,wl1273-st
35 - ti,wl1281-st
36 - ti,wl1283-st
37 - ti,wl1285-st
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