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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV
17 encoder clock source and contains additional TV TCON and DSI gates.
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
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/linux/drivers/clk/at91/
H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
33 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup() local
46 hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name); in of_sama5d2_clk_audio_pll_frac_setup()
53 "atmel,sama5d2-clk-audio-pll-frac",
59 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup() local
72 hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name); in of_sama5d2_clk_audio_pll_pad_setup()
79 "atmel,sama5d2-clk-audio-pll-pad",
85 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup() local
98 hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name); in of_sama5d2_clk_audio_pll_pmc_setup()
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/linux/drivers/clk/qcom/
H A Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
8 * and supplies fixed rate clocks as output to the networking hardware
13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
20 * and an output clock to NSS (network subsystem) at 300 MHZ. The other output
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/linux/drivers/clk/ti/
H A Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
179 const char *name; in ti_adpll_clk_get_name() local
183 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
184 "clock-output-names", in ti_adpll_clk_get_name()
186 &name); in ti_adpll_clk_get_name()
190 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
191 d->pa, postfix); in ti_adpll_clk_get_name()
194 return name; in ti_adpll_clk_get_name()
199 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
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/linux/Documentation/devicetree/bindings/mfd/
H A Dx-powers,ac100.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: X-Powers AC100
10 - Chen-Yu Tsai <wens@csie.org>
14 const: x-powers,ac100
23 "#clock-cells":
27 const: x-powers,ac100-codec
32 clock-output-names:
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H A Drockchip,rk817.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
21 - rockchip,rk809
22 - rockchip,rk817
30 '#clock-cells':
32 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
39 clock-names:
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/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt5 an multiplexers for various clock signals.
8 - compatible: shall be one of:
9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11 - reg: physical base address and size of the controller's register area.
12 - clocks: phandles corresponding to the clock names
13 - clock-names: names of the clock sources - depends on compatible string
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
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/linux/tools/perf/tests/shell/
H A Ddaemon.sh3 # SPDX-License-Identifier: GPL-2.0
8 local name=$2
10 local output=$4
25 if [ "${name}" != "${line_name}" ]; then
26 echo "FAILED: wrong name"
35 if [ "${output}" != "${line_output}" ]; then
36 echo "FAILED: wrong output"
54 local name=$2
57 local output=$5
77 if [ "${name}" != "${line_name}" ]; then
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/linux/drivers/comedi/drivers/
H A Damplc_dio200.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
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H A Damplc_dio200_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
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/linux/Documentation/devicetree/bindings/leds/
H A Dleds-lp55xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp55xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
27 - national,lp5521
28 - national,lp5523
29 - ti,lp55231
30 - ti,lp5562
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/linux/drivers/clk/st/
H A Dclkgen-fsyn.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
20 * Maximum input clock to the PLL before we divide it down by 2
70 const char *name; member
82 unsigned long output, struct stm_fs *fs);
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
186 { .name = "clk-s-d0-fs0-ch0", },
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/linux/Documentation/sound/cards/
H A Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
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/linux/Documentation/devicetree/bindings/clock/
H A Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 Preferred name is 'clock-<freq>' with <freq> being the output
18 frequency as defined in the 'clock-frequency' property.
[all …]
H A Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
18 <freq> being the output frequency.
[all …]
H A Dkeystone-gate.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "ti,keystone,psc-clock".
9 - #clock-cells : from common clock binding; shall be set to 0.
10 - clocks : parent clock phandle
11 - reg : psc control and domain address address space
12 - reg-names : psc control and domain registers
13 - domain-id : psc domain id needed to check the transition state register
16 - clock-output-names : From common clock binding to override the
17 default output clock name
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H A Dsamsung,exynos5410-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5410 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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/linux/drivers/clk/
H A Dclk-moxart.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MOXA ART SoCs clock driver.
11 #include <linux/clk-provider.h>
22 const char *name = node->name; in moxart_of_pll_clk_init() local
25 of_property_read_string(node, "clock-output-names", &name); in moxart_of_pll_clk_init()
43 hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1); in moxart_of_pll_clk_init()
45 pr_err("%pOF: failed to register clock\n", node); in moxart_of_pll_clk_init()
49 clk_hw_register_clkdev(hw, NULL, name); in moxart_of_pll_clk_init()
52 CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
62 const char *name = node->name; in moxart_of_apb_clk_init() local
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H A Dclk-si570.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2011 - 2021 Xilinx Inc.
14 #include <linux/clk-provider.h>
64 * @hw: Clock hw struct
69 * @n1: Clock divider N1
70 * @hs_div: Clock divider HSDIV
71 * @rfreq: Clock multiplier RFREQ
72 * @frequency: Current output frequency
90 * si570_get_divs() - Read clock dividers from HW
92 * @rfreq: Fractional multiplier (output)
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/linux/drivers/clk/keystone/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PLL clock driver for Keystone devices
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
42 * @clkod_mask: output divider mask
43 * @clkod_shift: output divider shift
64 * struct clk_pll - Main pll clock
79 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc()
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
12 description: |-
13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
[all …]
/linux/drivers/clk/mvebu/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell EBU SoC common clock handling
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
16 #include <linux/clk-provider.h>
39 * Armada XP and the Armada 375 SoC. The name of the function was
67 if ((high_bound - low_bound) <= 0) in kirkwood_fix_sscg_deviation()
72 * Spread percentage = 1/96 * (H - L) / H in kirkwood_fix_sscg_deviation()
83 freq_swing_half = (((u64)high_bound - (u64)low_bound) in kirkwood_fix_sscg_deviation()
89 system_clk -= freq_swing_half; in kirkwood_fix_sscg_deviation()
121 clk_data.clk_num = 2 + desc->num_ratios; in mvebu_coreclk_setup()
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/linux/drivers/clk/sifive/
H A Dsifive-prci.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "sifive-prci.h"
12 #include "fu540-prci.h"
13 #include "fu740-prci.h"
20 * __prci_readl() - read from a PRCI register
34 return readl_relaxed(pd->va + offs); in __prci_readl()
39 writel_relaxed(v, pd->va + offs); in __prci_writel()
42 /* WRPLL-related private functions */
45 * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
64 c->divr = v; in __prci_wrpll_unpack()
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
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/linux/Documentation/ABI/testing/
H A Dsysfs-ptp14 hardware clock registered into the PTP class driver
21 This file contains the name of the PTP hardware clock
24 name" and to help distinguish PHY based devices from
32 This file contains the PTP hardware clock's maximum
41 Write integer to re-configure it.
48 alarms offer by the PTP hardware clock.
55 channels offered by the PTP hardware clock.
62 output channels offered by the PTP hardware clock.
69 offered by the PTP hardware clock.
77 physical clock is in use. Setting the value creates
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