Lines Matching +full:clock +full:- +full:output +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
20 * Maximum input clock to the PLL before we divide it down by 2
70 const char *name; member
82 unsigned long output, struct stm_fs *fs);
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
186 { .name = "clk-s-d0-fs0-ch0", },
187 { .name = "clk-s-d0-fs0-ch1", },
188 { .name = "clk-s-d0-fs0-ch2", },
189 { .name = "clk-s-d0-fs0-ch3", },
198 { .name = "clk-s-d2-fs0-ch0", },
199 { .name = "clk-s-d2-fs0-ch1", },
200 { .name = "clk-s-d2-fs0-ch2", },
201 { .name = "clk-s-d2-fs0-ch3", },
210 { .name = "clk-s-d3-fs0-ch0", },
211 { .name = "clk-s-d3-fs0-ch1", },
212 { .name = "clk-s-d3-fs0-ch2", },
213 { .name = "clk-s-d3-fs0-ch3", },
222 * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
224 * Traits of this clock:
225 * prepare - clk_(un)prepare only ensures parent is (un)prepared
226 * enable - clk_enable and clk_disable are functional & control the Fsyn
227 * rate - inherits rate from parent. set_rate/round_rate/recalc_rate
228 * parent - fixed parent. No clk_set_parent support
232 * struct st_clk_quadfs_pll - A pll which outputs a fixed multiplier of
233 * its parent clock, found inside a type of
236 * @hw: handle between common and hardware-specific interfaces.
257 if (pll->lock) in quadfs_pll_enable()
258 spin_lock_irqsave(pll->lock, flags); in quadfs_pll_enable()
263 if (pll->data->reset_present) in quadfs_pll_enable()
267 * Use a fixed input clock noise bandwidth filter for the moment in quadfs_pll_enable()
269 if (pll->data->bwfilter_present) in quadfs_pll_enable()
273 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in quadfs_pll_enable()
278 CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity); in quadfs_pll_enable()
280 if (pll->lock) in quadfs_pll_enable()
281 spin_unlock_irqrestore(pll->lock, flags); in quadfs_pll_enable()
283 if (pll->data->lockstatus_present) in quadfs_pll_enable()
286 return -ETIMEDOUT; in quadfs_pll_enable()
298 if (pll->lock) in quadfs_pll_disable()
299 spin_lock_irqsave(pll->lock, flags); in quadfs_pll_disable()
305 CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity); in quadfs_pll_disable()
307 if (pll->data->reset_present) in quadfs_pll_disable()
310 if (pll->lock) in quadfs_pll_disable()
311 spin_unlock_irqrestore(pll->lock, flags); in quadfs_pll_disable()
319 return pll->data->powerup_polarity ? !npda : !!npda; in quadfs_pll_is_enabled()
325 unsigned long nd = fs->ndiv + 16; /* ndiv value */ in clk_fs660c32_vco_get_rate()
344 pll->ndiv = params.ndiv; in quadfs_pll_fs660c32_recalc_rate()
350 unsigned long output, struct stm_fs *fs) in clk_fs660c32_vco_get_params() argument
358 /* Output clock range: 384Mhz to 660Mhz */ in clk_fs660c32_vco_get_params()
359 if (output < 384000000 || output > 660000000) in clk_fs660c32_vco_get_params()
360 return -EINVAL; in clk_fs660c32_vco_get_params()
365 return -EINVAL; in clk_fs660c32_vco_get_params()
368 output /= 1000; in clk_fs660c32_vco_get_params()
370 n = output * pdiv / input; in clk_fs660c32_vco_get_params()
373 fs->ndiv = n - 16; /* Converting formula value to reg value */ in clk_fs660c32_vco_get_params()
383 if (clk_fs660c32_vco_get_params(req->best_parent_rate, req->rate, ¶ms)) in quadfs_pll_fs660c32_determine_rate()
386 clk_fs660c32_vco_get_rate(req->best_parent_rate, ¶ms, &req->rate); in quadfs_pll_fs660c32_determine_rate()
390 req->rate, (unsigned int)params.ndiv); in quadfs_pll_fs660c32_determine_rate()
405 return -EINVAL; in quadfs_pll_fs660c32_set_rate()
418 return -EINVAL; in quadfs_pll_fs660c32_set_rate()
420 pll->ndiv = params.ndiv; in quadfs_pll_fs660c32_set_rate()
422 if (pll->lock) in quadfs_pll_fs660c32_set_rate()
423 spin_lock_irqsave(pll->lock, flags); in quadfs_pll_fs660c32_set_rate()
425 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in quadfs_pll_fs660c32_set_rate()
427 if (pll->lock) in quadfs_pll_fs660c32_set_rate()
428 spin_unlock_irqrestore(pll->lock, flags); in quadfs_pll_fs660c32_set_rate()
443 const char *name, const char *parent_name, in st_clk_register_quadfs_pll() argument
454 if (WARN_ON(!name || !parent_name)) in st_clk_register_quadfs_pll()
455 return ERR_PTR(-EINVAL); in st_clk_register_quadfs_pll()
459 return ERR_PTR(-ENOMEM); in st_clk_register_quadfs_pll()
461 init.name = name; in st_clk_register_quadfs_pll()
462 init.ops = quadfs->pll_ops; in st_clk_register_quadfs_pll()
467 pll->data = quadfs; in st_clk_register_quadfs_pll()
468 pll->regs_base = reg; in st_clk_register_quadfs_pll()
469 pll->lock = lock; in st_clk_register_quadfs_pll()
470 pll->hw.init = &init; in st_clk_register_quadfs_pll()
472 clk = clk_register(NULL, &pll->hw); in st_clk_register_quadfs_pll()
483 * Traits of this clock:
484 * prepare - clk_(un)prepare only ensures parent is (un)prepared
485 * enable - clk_enable and clk_disable are functional
486 * rate - set rate is functional
487 * parent - fixed parent. No clk_set_parent support
491 * struct st_clk_quadfs_fsynth - One clock output from a four channel digital
494 * @hw: handle between common and hardware-specific interfaces
496 * @nsb: regmap field in the output control register for the digital
500 * @nsdiv: regmap field in the output control register for
519 * 2. It restores the clock rate when a driver does an enable
538 CLKGEN_WRITE(fs, en[fs->chan], 1); in quadfs_fsynth_program_enable()
539 CLKGEN_WRITE(fs, en[fs->chan], 0); in quadfs_fsynth_program_enable()
549 * when fine tuning the speed of a running clock. in quadfs_fsynth_program_rate()
551 CLKGEN_WRITE(fs, en[fs->chan], 0); in quadfs_fsynth_program_rate()
553 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md); in quadfs_fsynth_program_rate()
554 CLKGEN_WRITE(fs, pe[fs->chan], fs->pe); in quadfs_fsynth_program_rate()
555 CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv); in quadfs_fsynth_program_rate()
557 if (fs->lock) in quadfs_fsynth_program_rate()
558 spin_lock_irqsave(fs->lock, flags); in quadfs_fsynth_program_rate()
560 if (fs->data->nsdiv_present) in quadfs_fsynth_program_rate()
561 CLKGEN_WRITE(fs, nsdiv[fs->chan], fs->nsdiv); in quadfs_fsynth_program_rate()
563 if (fs->lock) in quadfs_fsynth_program_rate()
564 spin_unlock_irqrestore(fs->lock, flags); in quadfs_fsynth_program_rate()
576 if (fs->lock) in quadfs_fsynth_enable()
577 spin_lock_irqsave(fs->lock, flags); in quadfs_fsynth_enable()
579 CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity); in quadfs_fsynth_enable()
581 if (fs->data->nrst_present) in quadfs_fsynth_enable()
582 CLKGEN_WRITE(fs, nrst[fs->chan], 0); in quadfs_fsynth_enable()
584 if (fs->lock) in quadfs_fsynth_enable()
585 spin_unlock_irqrestore(fs->lock, flags); in quadfs_fsynth_enable()
599 if (fs->lock) in quadfs_fsynth_disable()
600 spin_lock_irqsave(fs->lock, flags); in quadfs_fsynth_disable()
602 CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity); in quadfs_fsynth_disable()
604 if (fs->lock) in quadfs_fsynth_disable()
605 spin_unlock_irqrestore(fs->lock, flags); in quadfs_fsynth_disable()
611 u32 nsb = CLKGEN_READ(fs, nsb[fs->chan]); in quadfs_fsynth_is_enabled()
616 return fs->data->standby_polarity ? !nsb : !!nsb; in quadfs_fsynth_is_enabled()
624 unsigned long s = (1 << fs->sdiv); in clk_fs660c32_dig_get_rate()
636 ns = (fs->nsdiv == 1) ? 1 : 3; in clk_fs660c32_dig_get_rate()
638 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns; in clk_fs660c32_dig_get_rate()
646 signed long input, unsigned long output, uint64_t *p, in clk_fs660c32_get_pe() argument
653 val = (uint64_t)output << si; in clk_fs660c32_get_pe()
655 *p = (uint64_t)input * P20 - (32LL + (uint64_t)m) * val * (P20 / 32LL); in clk_fs660c32_get_pe()
669 new_deviation = abs(output - new_freq); in clk_fs660c32_get_pe()
672 fs->mdiv = m; in clk_fs660c32_get_pe()
673 fs->pe = (unsigned long)*p; in clk_fs660c32_get_pe()
674 fs->sdiv = si; in clk_fs660c32_get_pe()
675 fs->nsdiv = 1; in clk_fs660c32_get_pe()
682 unsigned long output, struct stm_fs *fs) in clk_fs660c32_dig_get_params() argument
698 input, output, &p1, fs); in clk_fs660c32_dig_get_params()
700 input, output, &p2, fs); in clk_fs660c32_dig_get_params()
709 input, output, &p, fs); in clk_fs660c32_dig_get_params()
714 return -1; in clk_fs660c32_dig_get_params()
716 /* pe fine tuning if deviation not 0: +/- 2 around computed pe value */ in clk_fs660c32_dig_get_params()
718 fs_tmp.mdiv = fs->mdiv; in clk_fs660c32_dig_get_params()
719 fs_tmp.sdiv = fs->sdiv; in clk_fs660c32_dig_get_params()
720 fs_tmp.nsdiv = fs->nsdiv; in clk_fs660c32_dig_get_params()
722 if (fs->pe > 2) in clk_fs660c32_dig_get_params()
723 p2 = fs->pe - 2; in clk_fs660c32_dig_get_params()
727 for (; p2 < 32768ll && (p2 <= (fs->pe + 2)); p2++) { in clk_fs660c32_dig_get_params()
732 new_deviation = abs(output - new_freq); in clk_fs660c32_dig_get_params()
736 fs->pe = (unsigned long)p2; in clk_fs660c32_dig_get_params()
751 params->mdiv = CLKGEN_READ(fs, mdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
752 params->pe = CLKGEN_READ(fs, pe[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
753 params->sdiv = CLKGEN_READ(fs, sdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
755 if (fs->data->nsdiv_present) in quadfs_fsynt_get_hw_value_for_recalc()
756 params->nsdiv = CLKGEN_READ(fs, nsdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
758 params->nsdiv = 1; in quadfs_fsynt_get_hw_value_for_recalc()
761 * If All are NULL then assume no clock rate is programmed. in quadfs_fsynt_get_hw_value_for_recalc()
763 if (!params->mdiv && !params->pe && !params->sdiv) in quadfs_fsynt_get_hw_value_for_recalc()
766 fs->md = params->mdiv; in quadfs_fsynt_get_hw_value_for_recalc()
767 fs->pe = params->pe; in quadfs_fsynt_get_hw_value_for_recalc()
768 fs->sdiv = params->sdiv; in quadfs_fsynt_get_hw_value_for_recalc()
769 fs->nsdiv = params->nsdiv; in quadfs_fsynt_get_hw_value_for_recalc()
783 clk_fs_get_rate = fs->data->get_rate; in quadfs_find_best_rate()
784 clk_fs_get_params = fs->data->get_params; in quadfs_find_best_rate()
801 clk_fs_get_rate = fs->data->get_rate; in quadfs_recalc_rate()
821 req->rate = quadfs_find_best_rate(hw, req->rate, in quadfs_determine_rate()
822 req->best_parent_rate, ¶ms); in quadfs_determine_rate()
826 req->rate, (unsigned int)params.sdiv, in quadfs_determine_rate()
837 fs->md = params->mdiv; in quadfs_program_and_enable()
838 fs->pe = params->pe; in quadfs_program_and_enable()
839 fs->sdiv = params->sdiv; in quadfs_program_and_enable()
840 fs->nsdiv = params->nsdiv; in quadfs_program_and_enable()
858 return -EINVAL; in quadfs_set_rate()
864 return -EINVAL; in quadfs_set_rate()
883 const char *name, const char *parent_name, in st_clk_register_quadfs_fsynth() argument
894 if (WARN_ON(!name || !parent_name)) in st_clk_register_quadfs_fsynth()
895 return ERR_PTR(-EINVAL); in st_clk_register_quadfs_fsynth()
899 return ERR_PTR(-ENOMEM); in st_clk_register_quadfs_fsynth()
901 init.name = name; in st_clk_register_quadfs_fsynth()
907 fs->data = quadfs; in st_clk_register_quadfs_fsynth()
908 fs->regs_base = reg; in st_clk_register_quadfs_fsynth()
909 fs->chan = chan; in st_clk_register_quadfs_fsynth()
910 fs->lock = lock; in st_clk_register_quadfs_fsynth()
911 fs->hw.init = &init; in st_clk_register_quadfs_fsynth()
913 clk = clk_register(NULL, &fs->hw); in st_clk_register_quadfs_fsynth()
933 clk_data->clk_num = QUADFS_MAX_CHAN; in st_of_create_quadfs_fsynths()
934 clk_data->clks = kcalloc(QUADFS_MAX_CHAN, sizeof(struct clk *), in st_of_create_quadfs_fsynths()
937 if (!clk_data->clks) { in st_of_create_quadfs_fsynths()
947 if (quadfs->outputs) { in st_of_create_quadfs_fsynths()
948 clk_name = quadfs->outputs[fschan].name; in st_of_create_quadfs_fsynths()
949 flags = quadfs->outputs[fschan].flags; in st_of_create_quadfs_fsynths()
952 "clock-output-names", in st_of_create_quadfs_fsynths()
959 * If we read an empty clock name then the channel is unused in st_of_create_quadfs_fsynths()
965 quadfs->data, reg, fschan, in st_of_create_quadfs_fsynths()
969 * If there was an error registering this clock output, clean in st_of_create_quadfs_fsynths()
973 clk_data->clks[fschan] = clk; in st_of_create_quadfs_fsynths()
1022 clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, datac->data, in st_of_quadfs_setup()
1036 kfree(pll_name); /* No longer need local copy of the PLL name */ in st_of_quadfs_setup()
1044 CLK_OF_DECLARE(quadfs660C, "st,quadfs-pll", st_of_quadfs660C_setup);
1058 CLK_OF_DECLARE(quadfs660D0, "st,quadfs-d0", st_of_quadfs660D0_setup);
1065 CLK_OF_DECLARE(quadfs660D2, "st,quadfs-d2", st_of_quadfs660D2_setup);
1072 CLK_OF_DECLARE(quadfs660D3, "st,quadfs-d3", st_of_quadfs660D3_setup);