| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | mediatek,smi-common.txt | 6 which generation the SoCs use:
7 generation 1: mt2701 and mt7623.
8 generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
10 There's slight differences between the two SMI, for generation 2, the
12 for generation 1, the register is at smi ao base(smi always on register
13 base). Besides that, the smi async clock should be prepared and enabled for
14 SMI generation 1 to transform the smi clock into emi clock domain, but that is
15 not needed for SMI generation 2.
18 - compatible : must be one of :
19 "mediatek,mt2701-smi-common"
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| H A D | mediatek,smi-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
17 which generation the SoCs use:
18 generation 1: mt2701 and mt7623.
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
21 There's slight differences between the two SMI, for generation 2, the
23 for generation 1, the register is at smi ao base(smi always on register
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | imx7ulp-scg-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
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| H A D | imx7ulp-clock.txt | 1 * Clock bindings for Freescale i.MX7ULP
3 i.MX7ULP Clock functions are under joint control of the System
4 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
8 and A7 domain. Except for a few clock sources shared between two
9 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
10 and and the Fast IRC clock (FIRCLK), clock sources and clock
13 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
14 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
16 Note: this binding doc is only for A7 clock domain.
18 System Clock Generation (SCG) modules:
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| H A D | sophgo,sg2042-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 PLL Clock Generator
10 - Chen Wang <unicorn_wang@outlook.com>
14 const: sophgo,sg2042-pll
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
[all …]
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| H A D | imx8ulp-cgc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8ULP Clock Generation & Control(CGC) Module
10 - Jacky Bai <ping.bai@nxp.com>
13 On i.MX8ULP, The clock sources generation, distribution and management is
20 - fsl,imx8ulp-cgc1
21 - fsl,imx8ulp-cgc2
26 '#clock-cells':
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| H A D | renesas,rzv2h-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
14 and control of clock signals for the IP modules, generation and control of resets,
19 const: renesas,r9a09g057-cpg
26 - description: AUDIO_EXTAL clock input
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| H A D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| H A D | imx8ulp-pcc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module
10 - Jacky Bai <ping.bai@nxp.com>
13 On i.MX8ULP, The clock sources generation, distribution and management is
15 software reset, clock selection, optional division and clock gating mode
21 - fsl,imx8ulp-pcc3
22 - fsl,imx8ulp-pcc4
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| H A D | apple,nco.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apple,nco.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Povišer <povik+lin@cutebit.org>
14 such as the t8103 (M1) is a programmable clock generator performing
15 fractional division of a high frequency input clock.
18 generation of audio bitclocks.
23 - enum:
24 - apple,t6000-nco
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| H A D | intel,cgu-lgm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC's Clock Controller(CGU)
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
17 Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
23 const: intel,cgu-lgm
28 '#clock-cells':
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| H A D | imx7ulp-pcc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | mediatek,iommu.txt | 4 this M4U have two generations of HW architecture. Generation one uses flat
5 pagetable, and only supports 4K size page mapping. Generation two uses the
6 ARM Short-Descriptor translation table format for address translation.
14 +--------+
16 gals0-rx gals1-rx (Global Async Local Sync rx)
19 gals0-tx gals1-tx (Global Async Local Sync tx)
21 +--------+
25 +----------------+-------
27 | gals-rx There may be GALS in some larbs.
30 | gals-tx
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| H A D | mediatek,iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/contrib/ntp/ntpd/ |
| H A D | ntp.conf.mdoc.in | 6 .\" It has been AutoGen-ed May 25, 2024 at 12:03:50 AM by AutoGen 5.18.16
8 .\" and the template file agmdoc-cmd.tpl
14 .Op Fl \-option\-name
15 .Op Fl \-option\-name Ar value
46 host addresses written in numeric, dotted\-quad form,
62 .Bl -bullet -offset indent
72 .Sx Reference Clock Suppor
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| H A D | ntp.conf.5mdoc | 6 .\" It has been AutoGen-ed May 25, 2024 at 12:03:50 AM by AutoGen 5.18.16
8 .\" and the template file agmdoc-cmd.tpl
14 .Op Fl \-option\-name
15 .Op Fl \-option\-name Ar value
46 host addresses written in numeric, dotted\-quad form,
62 .Bl -bullet -offset indent
72 .Sx Reference Clock Suppor
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| H A D | ntp.conf.5man | 2 . it 1 an-trap
6 .ds B-Font [CB]
7 .ds I-Font [CI]
8 .ds R-Font [CR]
10 .ds B-Font B
11 .ds I-Font I
12 .ds R-Font R
15 .\" EDIT THIS FILE WITH CAUTION (in-mem file)
17 .\" It has been AutoGen-ed May 25, 2024 at 12:04:03 AM by AutoGen 5.18.16
19 .\" and the template file agman-cm
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| H A D | ntp.conf.man.in | 2 . it 1 an-trap
6 .ds B-Font [CB]
7 .ds I-Font [CI]
8 .ds R-Font [CR]
10 .ds B-Font B
11 .ds I-Font I
12 .ds R-Font R
15 .\" EDIT THIS FILE WITH CAUTION (in-mem file)
17 .\" It has been AutoGen-ed May 25, 2024 at 12:04:03 AM by AutoGen 5.18.16
19 .\" and the template file agman-cm
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| H A D | ntp.conf.def | 1 /* -*- Mode: Text -*- */
7 // We want the synopsis to be "/etc/ntp.conf" but we need the prog-name
8 // to be ntp.conf - the latter is also how autogen produces the output
10 prog-name = "ntp.conf";
11 file-path = "/etc/ntp.conf";
12 prog-title = "Network Time Protocol daemon (ntpd) configuration format";
15 explain = <<- _END_EXPLAIN
18 doc-section = {
19 ds-type = 'DESCRIPTION';
20 ds-format = 'mdoc';
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| H A D | invoke-ntp.conf.texi | 7 # EDIT THIS FILE WITH CAUTION (invoke-ntp.conf.texi)
9 # It has been AutoGen-ed May 25, 2024 at 12:03:56 AM by AutoGen 5.18.16
11 # and the template file agtexi-file.tpl
27 @code{-c}
42 host addresses written in numeric, dotted-quad form,
68 @ref{Reference Clock Support}
93 clock, and auxiliary commands that specify environmental variables
101 class D), or (r) a reference clock address (127.127.x.x).
108 If the Basic Socket Interface Extensions for IPv6 (RFC-2553)
124 with the exception of reference clock addresse
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | rcar-gen2-phy.txt | 1 * Renesas R-Car generation 2 USB PHY
3 This file provides information on what the device node for the R-Car generation
7 - compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC.
8 "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
9 "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
10 "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
11 "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
12 "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
13 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
14 "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
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| H A D | rcar-gen3-phy-pcie.txt | 1 * Renesas R-Car generation 3 PCIe PHY
3 This file provides information on what the device node for the R-Car
4 generation 3 PCIe PHY contains.
7 - compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the
9 - reg: offset and length of the register block.
10 - clocks: clock phandle and specifier pair.
11 - power-domains: power domain phandle and specifier pair.
12 - resets: reset phandle and specifier pair.
13 - #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
15 Example (R-Car V3H):
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| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | nxp,tpm-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
14 and the generation of PWM signals to control electric motor and power
16 are clocked by an asynchronous clock that can remain enabled in low
23 - const: fsl,imx7ulp-tpm
24 - items:
25 - const: fsl,imx8ulp-tpm
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | sja1105.txt | 6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
25 - sja1105,role-phy:
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