Lines Matching +full:clock +full:- +full:generation

6 which generation the SoCs use:
7 generation 1: mt2701 and mt7623.
8 generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
10 There's slight differences between the two SMI, for generation 2, the
12 for generation 1, the register is at smi ao base(smi always on register
13 base). Besides that, the smi async clock should be prepared and enabled for
14 SMI generation 1 to transform the smi clock into emi clock domain, but that is
15 not needed for SMI generation 2.
18 - compatible : must be one of :
19 	"mediatek,mt2701-smi-common"
20 	"mediatek,mt2712-smi-common"
21 	"mediatek,mt6779-smi-common"
22 	"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
23 	"mediatek,mt8167-smi-common"
24 	"mediatek,mt8173-smi-common"
25 	"mediatek,mt8183-smi-common"
26 - reg : the register and size of the SMI block.
27 - power-domains : a phandle to the power domain of this local arbiter.
28 - clocks : Must contain an entry for each entry in clock-names.
29 - clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
30   for generation 2 smi HW as follows:
31   - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
33   - "smi" : It's the clock for transfer data and command.
35   - "async" : asynchronous clock, it help transform the smi clock into the emi
36 	      clock domain, this clock is only needed by generation 1 smi HW.
37   and these 2 option clocks for generation 2 smi HW:
38   - "gals0": the path0 clock of GALS(Global Async Local Sync).
39   - "gals1": the path1 clock of GALS(Global Async Local Sync).
44 		compatible = "mediatek,mt8173-smi-common";
46 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
49 		clock-names = "apb", "smi";